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9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#ifndef CONFIG_SYS_MONITOR_BASE
13#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
14#endif
15
16#ifndef CONFIG_RESET_VECTOR_ADDRESS
17#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
18#endif
19
20
21
22#define CONFIG_PCI_INDIRECT_BRIDGE
23#define CONFIG_PCIE1
24#define CONFIG_PCIE2
25#define CONFIG_PCIE3
26#define CONFIG_FSL_PCI_INIT
27#define CONFIG_FSL_PCIE_RESET
28#define CONFIG_SYS_PCI_64BIT
29
30#ifndef __ASSEMBLY__
31extern unsigned long get_clock_freq(void);
32#endif
33
34#define CONFIG_SYS_CLK_FREQ 66666666
35#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
36
37
38
39
40#define CONFIG_L2_CACHE
41#define CONFIG_BTB
42#define CONFIG_HWCONFIG
43
44#define CONFIG_ENABLE_36BIT_PHYS
45
46#define CONFIG_SYS_MEMTEST_START 0x01000000
47#define CONFIG_SYS_MEMTEST_END 0x02000000
48
49
50#define CONFIG_SYS_LBC_LBCR 0x00000000
51#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
52
53
54#define CONFIG_VERY_BIG_RAM
55#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
56#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
57
58#define CONFIG_DIMM_SLOTS_PER_CTLR 1
59#define CONFIG_CHIP_SELECTS_PER_CTRL 1
60
61#define CONFIG_DDR_SPD
62#define CONFIG_FSL_DDR_INTERACTIVE
63#define CONFIG_SYS_SDRAM_SIZE 512u
64#define CONFIG_SYS_SPD_BUS_NUM 0
65#define SPD_EEPROM_ADDRESS 0x50
66#define CONFIG_SYS_DDR_RAW_TIMING
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87
88#define CONFIG_SYS_FLASH_BASE 0xec000000
89#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
90
91#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
92 | BR_PS_16 | BR_V)
93#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
94
95#define CONFIG_SYS_FLASH_EMPTY_INFO
96#define CONFIG_SYS_MAX_FLASH_BANKS 1
97#define CONFIG_SYS_MAX_FLASH_SECT 512
98#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
99#define CONFIG_SYS_FLASH_WRITE_TOUT 500
100
101#define CONFIG_SYS_INIT_RAM_LOCK
102#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
103#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
104#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
105 GENERATED_GBL_DATA_SIZE)
106#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
107
108#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
109#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
110
111#define CONFIG_SYS_NAND_BASE 0xffa00000
112#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
113
114#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
115#define CONFIG_SYS_MAX_NAND_DEVICE 1
116#define CONFIG_NAND_FSL_ELBC
117#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
118
119
120#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
121 | (2<<BR_DECC_SHIFT) \
122 | BR_PS_8 \
123 | BR_MS_FCM \
124 | BR_V)
125#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
126 | OR_FCM_PGS \
127 | OR_FCM_CSCT \
128 | OR_FCM_CST \
129 | OR_FCM_CHT \
130 | OR_FCM_SCY_1 \
131 | OR_FCM_TRLX \
132 | OR_FCM_EHTR)
133
134#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
135#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
136#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
137#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
138
139
140#undef CONFIG_SERIAL_SOFTWARE_FIFO
141#define CONFIG_SYS_NS16550_SERIAL
142#define CONFIG_SYS_NS16550_REG_SIZE 1
143#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
144
145#define CONFIG_SYS_BAUDRATE_TABLE \
146 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
147
148#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
149#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
150
151
152#define CONFIG_SYS_I2C
153#define CONFIG_SYS_I2C_FSL
154#define CONFIG_SYS_FSL_I2C_SPEED 400000
155#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
156#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
157#define CONFIG_SYS_FSL_I2C2_SPEED 400000
158#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
159#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
160
161
162
163
164#define CONFIG_ID_EEPROM
165#ifdef CONFIG_ID_EEPROM
166#define CONFIG_SYS_I2C_EEPROM_NXID
167#endif
168#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
169#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
170#define CONFIG_SYS_EEPROM_BUS_NUM 0
171
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177
178#define CONFIG_SYS_PCIE3_NAME "Slot 3"
179#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
180#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
181#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
182#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
183#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
184#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
185#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
186#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
187
188
189#define CONFIG_SYS_PCIE2_NAME "Slot 2"
190#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
191#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
192#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
193#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
194#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
195#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
196#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
197#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
198
199
200#define CONFIG_SYS_PCIE1_NAME "Slot 1"
201#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
202#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
203#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
204#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
205#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
206#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
207#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
208#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
209
210#if defined(CONFIG_PCI)
211#define CONFIG_PCI_SCAN_SHOW
212#endif
213
214
215
216
217#define CONFIG_ENV_OVERWRITE
218
219#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
220#define CONFIG_ENV_SIZE 0x2000
221#define CONFIG_ENV_SECT_SIZE 0x20000
222
223#define CONFIG_LOADS_ECHO
224#define CONFIG_SYS_LOADS_BAUD_CHANGE
225
226
227
228
229#define CONFIG_HAS_FSL_DR_USB
230#ifdef CONFIG_HAS_FSL_DR_USB
231#ifdef CONFIG_USB_EHCI_HCD
232#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
233#define CONFIG_USB_EHCI_FSL
234#endif
235#endif
236
237
238
239
240#define CONFIG_SYS_LOAD_ADDR 0x2000000
241
242
243
244
245
246
247#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
248#define CONFIG_SYS_BOOTM_LEN (64 << 20)
249
250
251
252
253#define CONFIG_BOOTFILE "uImage"
254#define CONFIG_UBOOTPATH (u-boot.bin)
255
256
257#define CONFIG_LOADADDR 1000000
258
259
260#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
261#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
262#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
263#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
264#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
265#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
266#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
267#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
268 CONFIG_SYS_QMAN_CENA_SIZE)
269#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
270#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
271#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
272#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
273#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
274#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
275#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
276#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
277#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
278#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
279 CONFIG_SYS_BMAN_CENA_SIZE)
280#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
281#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
282
283
284#define CONFIG_SYS_DPAA_FMAN
285
286#ifdef CONFIG_SYS_DPAA_FMAN
287#define CONFIG_FMAN_ENET
288#define CONFIG_PHY_ATHEROS
289#endif
290
291
292
293#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
294#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
295#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
296#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
297
298#ifdef CONFIG_FMAN_ENET
299#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
300#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
301
302#define CONFIG_SYS_TBIPA_VALUE 8
303#define CONFIG_ETHPRIME "FM1@DTSEC1"
304#endif
305
306#define CONFIG_EXTRA_ENV_SETTINGS \
307 "netdev=eth0\0" \
308 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
309 "loadaddr=1000000\0" \
310 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
311 "tftpflash=tftpboot $loadaddr $uboot; " \
312 "protect off $ubootaddr +$filesize; " \
313 "erase $ubootaddr +$filesize; " \
314 "cp.b $loadaddr $ubootaddr $filesize; " \
315 "protect on $ubootaddr +$filesize; " \
316 "cmp.b $loadaddr $ubootaddr $filesize\0" \
317 "consoledev=ttyS0\0" \
318 "ramdiskaddr=2000000\0" \
319 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
320 "fdtaddr=1e00000\0" \
321 "fdtfile=p1023rdb.dtb\0" \
322 "othbootargs=ramdisk_size=600000\0" \
323 "bdev=sda1\0" \
324 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
325
326#define CONFIG_HDBOOT \
327 "setenv bootargs root=/dev/$bdev rw " \
328 "console=$consoledev,$baudrate $othbootargs;" \
329 "tftp $loadaddr $bootfile;" \
330 "tftp $fdtaddr $fdtfile;" \
331 "bootm $loadaddr - $fdtaddr"
332
333#define CONFIG_NFSBOOTCOMMAND \
334 "setenv bootargs root=/dev/nfs rw " \
335 "nfsroot=$serverip:$rootpath " \
336 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
337 "console=$consoledev,$baudrate $othbootargs;" \
338 "tftp $loadaddr $bootfile;" \
339 "tftp $fdtaddr $fdtfile;" \
340 "bootm $loadaddr - $fdtaddr"
341
342#define CONFIG_RAMBOOTCOMMAND \
343 "setenv bootargs root=/dev/ram rw " \
344 "console=$consoledev,$baudrate $othbootargs;" \
345 "tftp $ramdiskaddr $ramdiskfile;" \
346 "tftp $loadaddr $bootfile;" \
347 "tftp $fdtaddr $fdtfile;" \
348 "bootm $loadaddr $ramdiskaddr $fdtaddr"
349
350#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
351
352#endif
353