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13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#define CONFIG_PCIE1
17#define CONFIG_PCIE2
18#define CONFIG_FSL_PCI_INIT
19#define CONFIG_PCI_INDIRECT_BRIDGE
20#define CONFIG_FSL_PCIE_RESET
21#define CONFIG_SYS_PCI_64BIT
22
23#if defined(CONFIG_TARTGET_UCP1020T1)
24
25#define CONFIG_UCP1020_REV_1_3
26
27#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
28
29#define CONFIG_TSEC1
30#define CONFIG_TSEC3
31#define CONFIG_HAS_ETH0
32#define CONFIG_HAS_ETH1
33#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
34#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
35#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
36#define CONFIG_IPADDR 10.80.41.229
37#define CONFIG_SERVERIP 10.80.41.227
38#define CONFIG_NETMASK 255.255.252.0
39#define CONFIG_ETHPRIME "eTSEC3"
40
41#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
42
43#define CONFIG_SYS_L2_SIZE (256 << 10)
44
45#endif
46
47#if defined(CONFIG_TARGET_UCP1020)
48
49#define CONFIG_UCP1020
50#define CONFIG_UCP1020_REV_1_3
51
52#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
53
54#define CONFIG_TSEC1
55#define CONFIG_TSEC2
56#define CONFIG_TSEC3
57#define CONFIG_HAS_ETH0
58#define CONFIG_HAS_ETH1
59#define CONFIG_HAS_ETH2
60#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
61#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
62#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
63#define CONFIG_IPADDR 192.168.1.81
64#define CONFIG_IPADDR1 192.168.1.82
65#define CONFIG_IPADDR2 192.168.1.83
66#define CONFIG_SERVERIP 192.168.1.80
67#define CONFIG_GATEWAYIP 102.168.1.1
68#define CONFIG_NETMASK 255.255.255.0
69#define CONFIG_ETHPRIME "eTSEC1"
70
71#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
72
73#define CONFIG_SYS_L2_SIZE (256 << 10)
74
75#endif
76
77#ifdef CONFIG_SDCARD
78#define CONFIG_RAMBOOT_SDCARD
79#define CONFIG_SYS_RAMBOOT
80#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
81#endif
82
83#ifdef CONFIG_SPIFLASH
84#define CONFIG_RAMBOOT_SPIFLASH
85#define CONFIG_SYS_RAMBOOT
86#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
87#endif
88
89#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
90
91#ifndef CONFIG_RESET_VECTOR_ADDRESS
92#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
93#endif
94
95#ifndef CONFIG_SYS_MONITOR_BASE
96#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
97#endif
98
99#define CONFIG_ENV_OVERWRITE
100
101#define CONFIG_SYS_SATA_MAX_DEVICE 2
102#define CONFIG_LBA48
103
104#define CONFIG_SYS_CLK_FREQ 66666666
105#define CONFIG_DDR_CLK_FREQ 66666666
106
107#define CONFIG_HWCONFIG
108
109
110
111
112#define CONFIG_L2_CACHE
113#define CONFIG_BTB
114
115#define CONFIG_ENABLE_36BIT_PHYS
116
117#define CONFIG_SYS_MEMTEST_START 0x00200000
118#define CONFIG_SYS_MEMTEST_END 0x1fffffff
119
120#define CONFIG_SYS_CCSRBAR 0xffe00000
121#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
122
123
124
125#ifdef CONFIG_SPL_BUILD
126#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
127#endif
128
129
130#define CONFIG_DDR_ECC_ENABLE
131#ifndef CONFIG_DDR_ECC_ENABLE
132#define CONFIG_SYS_DDR_RAW_TIMING
133#define CONFIG_DDR_SPD
134#endif
135#define CONFIG_SYS_SPD_BUS_NUM 1
136#undef CONFIG_FSL_DDR_INTERACTIVE
137
138#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
139#define CONFIG_CHIP_SELECTS_PER_CTRL 1
140#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
141#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
142#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143
144#define CONFIG_DIMM_SLOTS_PER_CTLR 1
145
146
147#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
148#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
149#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
150#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
151#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
152#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
153
154#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
155#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
156#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
157#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
158
159#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
160#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
161#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
162#define CONFIG_SYS_DDR_RCW_1 0x00000000
163#define CONFIG_SYS_DDR_RCW_2 0x00000000
164#ifdef CONFIG_DDR_ECC_ENABLE
165#define CONFIG_SYS_DDR_CONTROL 0xE70C0000
166#else
167#define CONFIG_SYS_DDR_CONTROL 0xC70C0000
168#endif
169#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
170#define CONFIG_SYS_DDR_TIMING_4 0x00220001
171#define CONFIG_SYS_DDR_TIMING_5 0x03402400
172
173#define CONFIG_SYS_DDR_TIMING_3 0x00020000
174#define CONFIG_SYS_DDR_TIMING_0 0x00330004
175#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
176#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
177#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
178#define CONFIG_SYS_DDR_MODE_1 0x40461520
179#define CONFIG_SYS_DDR_MODE_2 0x8000c000
180#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
181
182#undef CONFIG_CLOCKS_IN_MHZ
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200#define CONFIG_SYS_MAX_FLASH_SECT 512
201#define CONFIG_SYS_FLASH_BASE 0xec000000
202
203#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204
205#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
206 | BR_PS_16 | BR_V)
207
208#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
209
210#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
211#define CONFIG_SYS_FLASH_QUIET_TEST
212#define CONFIG_FLASH_SHOW_PROGRESS 45
213
214#define CONFIG_SYS_MAX_FLASH_BANKS 1
215
216#undef CONFIG_SYS_FLASH_CHECKSUM
217#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
218#define CONFIG_SYS_FLASH_WRITE_TOUT 500
219
220#define CONFIG_SYS_FLASH_EMPTY_INFO
221
222#define CONFIG_SYS_INIT_RAM_LOCK
223#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
224
225#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
226#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
227#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
228
229#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
230
231#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
232 GENERATED_GBL_DATA_SIZE)
233#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
234
235#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
236#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
237
238#define CONFIG_SYS_PMC_BASE 0xff980000
239#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
240#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
241 BR_PS_8 | BR_V)
242#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
243 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
244 OR_GPCM_EAD)
245
246#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
247#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
248#ifdef CONFIG_NAND_FSL_ELBC
249#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
250#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
251#endif
252
253
254
255
256
257#undef CONFIG_SERIAL_SOFTWARE_FIFO
258#define CONFIG_SYS_NS16550_SERIAL
259#define CONFIG_SYS_NS16550_REG_SIZE 1
260#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
261#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
262#define CONFIG_NS16550_MIN_FUNCTIONS
263#endif
264
265#define CONFIG_SYS_BAUDRATE_TABLE \
266 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
267
268#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
269#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
270
271
272#define CONFIG_SYS_I2C
273#define CONFIG_SYS_I2C_FSL
274#define CONFIG_SYS_FSL_I2C_SPEED 400000
275#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
276#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
277#define CONFIG_SYS_FSL_I2C2_SPEED 400000
278#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
279#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
280#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
281#define CONFIG_SYS_SPD_BUS_NUM 1
282
283#define CONFIG_RTC_DS1337
284#define CONFIG_RTC_DS1337_NOOSC
285#define CONFIG_SYS_I2C_RTC_ADDR 0x68
286#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
287#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
288#define CONFIG_SYS_I2C_IDT6V49205B 0x69
289
290#define CONFIG_SF_DEFAULT_SPEED 10000000
291#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
292
293#if defined(CONFIG_PCI)
294
295
296
297
298
299
300#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
301#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
302#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
303#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
304#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
305#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
306#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
307#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
308#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
309
310
311#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
312#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
313#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
314#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
315#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
316#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
317#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
318#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
319#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
320
321#define CONFIG_PCI_SCAN_SHOW
322#endif
323
324
325
326
327#ifdef CONFIG_ENV_FIT_UCBOOT
328
329#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
330#define CONFIG_ENV_SIZE 0x20000
331#define CONFIG_ENV_SECT_SIZE 0x20000
332
333#else
334
335#define CONFIG_ENV_SPI_BUS 0
336#define CONFIG_ENV_SPI_CS 0
337#define CONFIG_ENV_SPI_MAX_HZ 10000000
338#define CONFIG_ENV_SPI_MODE 0
339
340#ifdef CONFIG_RAMBOOT_SPIFLASH
341
342#define CONFIG_ENV_SIZE 0x3000
343#define CONFIG_ENV_OFFSET 0x2000
344#define CONFIG_ENV_SECT_SIZE 0x1000
345
346#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
347
348#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
349#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
350#endif
351
352#elif defined(CONFIG_RAMBOOT_SDCARD)
353#define CONFIG_FSL_FIXED_MMC_LOCATION
354#define CONFIG_ENV_SIZE 0x2000
355#define CONFIG_SYS_MMC_ENV_DEV 0
356
357#elif defined(CONFIG_SYS_RAMBOOT)
358#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
359#define CONFIG_ENV_SIZE 0x2000
360
361#else
362#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
363#define CONFIG_ENV_SECT_SIZE 0x20000
364#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
365#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
366#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
367
368#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
369#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
370#endif
371
372#endif
373
374#endif
375
376#define CONFIG_LOADS_ECHO
377#define CONFIG_SYS_LOADS_BAUD_CHANGE
378
379
380
381
382#define CONFIG_HAS_FSL_DR_USB
383
384#if defined(CONFIG_HAS_FSL_DR_USB)
385#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
386
387#ifdef CONFIG_USB_EHCI_HCD
388#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
389#define CONFIG_USB_EHCI_FSL
390#endif
391#endif
392
393#undef CONFIG_WATCHDOG
394
395#ifdef CONFIG_MMC
396#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
397#define CONFIG_MMC_SPI
398#endif
399
400
401#undef CONFIG_WATCHDOG
402
403
404
405
406#define CONFIG_SYS_LOAD_ADDR 0x2000000
407#define CONFIG_SYS_HZ 1000
408
409
410
411
412
413
414#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
415#define CONFIG_SYS_BOOTM_LEN (64 << 20)
416
417#if defined(CONFIG_CMD_KGDB)
418#define CONFIG_KGDB_BAUDRATE 230400
419#define CONFIG_KGDB_SER_INDEX 2
420#endif
421
422
423
424
425
426#if defined(CONFIG_TSEC_ENET)
427
428#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
429#else
430#error "UCP1020 module revision is not defined !!!"
431#endif
432
433#define CONFIG_BOOTP_SERVERIP
434
435#define CONFIG_TSEC1_NAME "eTSEC1"
436#define CONFIG_TSEC2_NAME "eTSEC2"
437#define CONFIG_TSEC3_NAME "eTSEC3"
438
439#define TSEC1_PHY_ADDR 4
440#define TSEC2_PHY_ADDR 0
441#define TSEC2_PHY_ADDR_SGMII 0x00
442#define TSEC3_PHY_ADDR 6
443
444#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
445#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
446#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
447
448#define TSEC1_PHYIDX 0
449#define TSEC2_PHYIDX 0
450#define TSEC3_PHYIDX 0
451
452#endif
453
454#define CONFIG_HOSTNAME "UCP1020"
455#define CONFIG_ROOTPATH "/opt/nfsroot"
456#define CONFIG_BOOTFILE "uImage"
457#define CONFIG_UBOOTPATH u-boot.bin
458
459
460#define CONFIG_LOADADDR 1000000
461
462#if defined(CONFIG_DONGLE)
463
464#define CONFIG_EXTRA_ENV_SETTINGS \
465"bootcmd=run prog_spi_mbrbootcramfs\0" \
466"bootfile=uImage\0" \
467"consoledev=ttyS0\0" \
468"cramfsfile=image.cramfs\0" \
469"dtbaddr=0x00c00000\0" \
470"dtbfile=image.dtb\0" \
471"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
472"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
473"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
474"fileaddr=0x01000000\0" \
475"filesize=0x00080000\0" \
476"flashmbr=sf probe 0; " \
477 "tftp $loadaddr $mbr; " \
478 "sf erase $mbr_offset +$filesize; " \
479 "sf write $loadaddr $mbr_offset $filesize\0" \
480"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
481 "protect off $nor_recoveryaddr +$filesize; " \
482 "erase $nor_recoveryaddr +$filesize; " \
483 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
484 "protect on $nor_recoveryaddr +$filesize\0 " \
485"flashuboot=tftp $ubootaddr $ubootfile; " \
486 "protect off $nor_ubootaddr +$filesize; " \
487 "erase $nor_ubootaddr +$filesize; " \
488 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
489 "protect on $nor_ubootaddr +$filesize\0 " \
490"flashworking=tftp $workingaddr $cramfsfile; " \
491 "protect off $nor_workingaddr +$filesize; " \
492 "erase $nor_workingaddr +$filesize; " \
493 "cp.b $workingaddr $nor_workingaddr $filesize; " \
494 "protect on $nor_workingaddr +$filesize\0 " \
495"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
496"kerneladdr=0x01100000\0" \
497"kernelfile=uImage\0" \
498"loadaddr=0x01000000\0" \
499"mbr=uCP1020d.mbr\0" \
500"mbr_offset=0x00000000\0" \
501"mmbr=uCP1020Quiet.mbr\0" \
502"mmcpart=0:2\0" \
503"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
504 "mmc erase 1 1; " \
505 "mmc write $loadaddr 1 1\0" \
506"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
507 "mmc erase 0x40 0x400; " \
508 "mmc write $loadaddr 0x40 0x400\0" \
509"netdev=eth0\0" \
510"nor_recoveryaddr=0xEC0A0000\0" \
511"nor_ubootaddr=0xEFF80000\0" \
512"nor_workingaddr=0xECFA0000\0" \
513"norbootrecovery=setenv bootargs $recoverybootargs" \
514 " console=$consoledev,$baudrate $othbootargs; " \
515 "run norloadrecovery; " \
516 "bootm $kerneladdr - $dtbaddr\0" \
517"norbootworking=setenv bootargs $workingbootargs" \
518 " console=$consoledev,$baudrate $othbootargs; " \
519 "run norloadworking; " \
520 "bootm $kerneladdr - $dtbaddr\0" \
521"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
522 "setenv cramfsaddr $nor_recoveryaddr; " \
523 "cramfsload $dtbaddr $dtbfile; " \
524 "cramfsload $kerneladdr $kernelfile\0" \
525"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
526 "setenv cramfsaddr $nor_workingaddr; " \
527 "cramfsload $dtbaddr $dtbfile; " \
528 "cramfsload $kerneladdr $kernelfile\0" \
529"prog_spi_mbr=run spi__mbr\0" \
530"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
531"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
532 "run spi__cramfs\0" \
533"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
534 " console=$consoledev,$baudrate $othbootargs; " \
535 "tftp $rootfsaddr $rootfsfile; " \
536 "tftp $loadaddr $kernelfile; " \
537 "tftp $dtbaddr $dtbfile; " \
538 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
539"ramdisk_size=120000\0" \
540"ramdiskfile=rootfs.ext2.gz.uboot\0" \
541"recoveryaddr=0x02F00000\0" \
542"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
543"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
544 "mw.l 0xffe0f008 0x00400000\0" \
545"rootfsaddr=0x02F00000\0" \
546"rootfsfile=rootfs.ext2.gz.uboot\0" \
547"rootpath=/opt/nfsroot\0" \
548"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
549 "protect off 0xeC000000 +$filesize; " \
550 "erase 0xEC000000 +$filesize; " \
551 "cp.b $loadaddr 0xEC000000 $filesize; " \
552 "cmp.b $loadaddr 0xEC000000 $filesize; " \
553 "protect on 0xeC000000 +$filesize\0" \
554"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
555 "protect off 0xeFF80000 +$filesize; " \
556 "erase 0xEFF80000 +$filesize; " \
557 "cp.b $loadaddr 0xEFF80000 $filesize; " \
558 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
559 "protect on 0xeFF80000 +$filesize\0" \
560"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
561 "sf probe 0; sf erase 0x8000 +$filesize; " \
562 "sf write $loadaddr 0x8000 $filesize\0" \
563"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
564 "protect off 0xec0a0000 +$filesize; " \
565 "erase 0xeC0A0000 +$filesize; " \
566 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
567 "protect on 0xec0a0000 +$filesize\0" \
568"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
569 "sf probe 1; sf erase 0 +$filesize; " \
570 "sf write $loadaddr 0 $filesize\0" \
571"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
572 "sf probe 0; sf erase 0 +$filesize; " \
573 "sf write $loadaddr 0 $filesize\0" \
574"tftpflash=tftpboot $loadaddr $uboot; " \
575 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
576 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
577 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
578 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
579 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
580"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
581"ubootaddr=0x01000000\0" \
582"ubootfile=u-boot.bin\0" \
583"ubootd=u-boot4dongle.bin\0" \
584"upgrade=run flashworking\0" \
585"usb_phy_type=ulpi\0 " \
586"workingaddr=0x02F00000\0" \
587"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
588
589#else
590
591#if defined(CONFIG_UCP1020T1)
592
593#define CONFIG_EXTRA_ENV_SETTINGS \
594"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
595"bootfile=uImage\0" \
596"consoledev=ttyS0\0" \
597"cramfsfile=image.cramfs\0" \
598"dtbaddr=0x00c00000\0" \
599"dtbfile=image.dtb\0" \
600"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
601"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
602"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
603"fileaddr=0x01000000\0" \
604"filesize=0x00080000\0" \
605"flashmbr=sf probe 0; " \
606 "tftp $loadaddr $mbr; " \
607 "sf erase $mbr_offset +$filesize; " \
608 "sf write $loadaddr $mbr_offset $filesize\0" \
609"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
610 "protect off $nor_recoveryaddr +$filesize; " \
611 "erase $nor_recoveryaddr +$filesize; " \
612 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
613 "protect on $nor_recoveryaddr +$filesize\0 " \
614"flashuboot=tftp $ubootaddr $ubootfile; " \
615 "protect off $nor_ubootaddr +$filesize; " \
616 "erase $nor_ubootaddr +$filesize; " \
617 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
618 "protect on $nor_ubootaddr +$filesize\0 " \
619"flashworking=tftp $workingaddr $cramfsfile; " \
620 "protect off $nor_workingaddr +$filesize; " \
621 "erase $nor_workingaddr +$filesize; " \
622 "cp.b $workingaddr $nor_workingaddr $filesize; " \
623 "protect on $nor_workingaddr +$filesize\0 " \
624"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
625"kerneladdr=0x01100000\0" \
626"kernelfile=uImage\0" \
627"loadaddr=0x01000000\0" \
628"mbr=uCP1020.mbr\0" \
629"mbr_offset=0x00000000\0" \
630"netdev=eth0\0" \
631"nor_recoveryaddr=0xEC0A0000\0" \
632"nor_ubootaddr=0xEFF80000\0" \
633"nor_workingaddr=0xECFA0000\0" \
634"norbootrecovery=setenv bootargs $recoverybootargs" \
635 " console=$consoledev,$baudrate $othbootargs; " \
636 "run norloadrecovery; " \
637 "bootm $kerneladdr - $dtbaddr\0" \
638"norbootworking=setenv bootargs $workingbootargs" \
639 " console=$consoledev,$baudrate $othbootargs; " \
640 "run norloadworking; " \
641 "bootm $kerneladdr - $dtbaddr\0" \
642"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
643 "setenv cramfsaddr $nor_recoveryaddr; " \
644 "cramfsload $dtbaddr $dtbfile; " \
645 "cramfsload $kerneladdr $kernelfile\0" \
646"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
647 "setenv cramfsaddr $nor_workingaddr; " \
648 "cramfsload $dtbaddr $dtbfile; " \
649 "cramfsload $kerneladdr $kernelfile\0" \
650"othbootargs=quiet\0" \
651"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
652 " console=$consoledev,$baudrate $othbootargs; " \
653 "tftp $rootfsaddr $rootfsfile; " \
654 "tftp $loadaddr $kernelfile; " \
655 "tftp $dtbaddr $dtbfile; " \
656 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
657"ramdisk_size=120000\0" \
658"ramdiskfile=rootfs.ext2.gz.uboot\0" \
659"recoveryaddr=0x02F00000\0" \
660"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
661"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
662 "mw.l 0xffe0f008 0x00400000\0" \
663"rootfsaddr=0x02F00000\0" \
664"rootfsfile=rootfs.ext2.gz.uboot\0" \
665"rootpath=/opt/nfsroot\0" \
666"silent=1\0" \
667"tftpflash=tftpboot $loadaddr $uboot; " \
668 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
669 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
670 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
671 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
672 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
673"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
674"ubootaddr=0x01000000\0" \
675"ubootfile=u-boot.bin\0" \
676"upgrade=run flashworking\0" \
677"workingaddr=0x02F00000\0" \
678"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
679
680#else
681
682#define CONFIG_EXTRA_ENV_SETTINGS \
683"bootcmd=run norkernel\0" \
684"bootfile=uImage\0" \
685"consoledev=ttyS0\0" \
686"dtbaddr=0x00c00000\0" \
687"dtbfile=image.dtb\0" \
688"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
689"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
690"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
691"fileaddr=0x01000000\0" \
692"filesize=0x00080000\0" \
693"flashmbr=sf probe 0; " \
694 "tftp $loadaddr $mbr; " \
695 "sf erase $mbr_offset +$filesize; " \
696 "sf write $loadaddr $mbr_offset $filesize\0" \
697"flashuboot=tftp $loadaddr $ubootfile; " \
698 "protect off $nor_ubootaddr0 +$filesize; " \
699 "erase $nor_ubootaddr0 +$filesize; " \
700 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
701 "protect on $nor_ubootaddr0 +$filesize; " \
702 "protect off $nor_ubootaddr1 +$filesize; " \
703 "erase $nor_ubootaddr1 +$filesize; " \
704 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
705 "protect on $nor_ubootaddr1 +$filesize\0 " \
706"format0=protect off $part0base +$part0size; " \
707 "erase $part0base +$part0size\0" \
708"format1=protect off $part1base +$part1size; " \
709 "erase $part1base +$part1size\0" \
710"format2=protect off $part2base +$part2size; " \
711 "erase $part2base +$part2size\0" \
712"format3=protect off $part3base +$part3size; " \
713 "erase $part3base +$part3size\0" \
714"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
715"kerneladdr=0x01100000\0" \
716"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
717"kernelfile=uImage\0" \
718"loadaddr=0x01000000\0" \
719"mbr=uCP1020.mbr\0" \
720"mbr_offset=0x00000000\0" \
721"netdev=eth0\0" \
722"nor_ubootaddr0=0xEC000000\0" \
723"nor_ubootaddr1=0xEFF80000\0" \
724"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
725 "run norkernelload; " \
726 "bootm $kerneladdr - $dtbaddr\0" \
727"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
728 "setenv cramfsaddr $part0base; " \
729 "cramfsload $dtbaddr $dtbfile; " \
730 "cramfsload $kerneladdr $kernelfile\0" \
731"part0base=0xEC100000\0" \
732"part0size=0x00700000\0" \
733"part1base=0xEC800000\0" \
734"part1size=0x02000000\0" \
735"part2base=0xEE800000\0" \
736"part2size=0x00800000\0" \
737"part3base=0xEF000000\0" \
738"part3size=0x00F80000\0" \
739"partENVbase=0xEC080000\0" \
740"partENVsize=0x00080000\0" \
741"program0=tftp part0-000000.bin; " \
742 "protect off $part0base +$filesize; " \
743 "erase $part0base +$filesize; " \
744 "cp.b $loadaddr $part0base $filesize; " \
745 "echo Verifying...; " \
746 "cmp.b $loadaddr $part0base $filesize\0" \
747"program1=tftp part1-000000.bin; " \
748 "protect off $part1base +$filesize; " \
749 "erase $part1base +$filesize; " \
750 "cp.b $loadaddr $part1base $filesize; " \
751 "echo Verifying...; " \
752 "cmp.b $loadaddr $part1base $filesize\0" \
753"program2=tftp part2-000000.bin; " \
754 "protect off $part2base +$filesize; " \
755 "erase $part2base +$filesize; " \
756 "cp.b $loadaddr $part2base $filesize; " \
757 "echo Verifying...; " \
758 "cmp.b $loadaddr $part2base $filesize\0" \
759"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
760 " console=$consoledev,$baudrate $othbootargs; " \
761 "tftp $rootfsaddr $rootfsfile; " \
762 "tftp $loadaddr $kernelfile; " \
763 "tftp $dtbaddr $dtbfile; " \
764 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
765"ramdisk_size=120000\0" \
766"ramdiskfile=rootfs.ext2.gz.uboot\0" \
767"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
768 "mw.l 0xffe0f008 0x00400000\0" \
769"rootfsaddr=0x02F00000\0" \
770"rootfsfile=rootfs.ext2.gz.uboot\0" \
771"rootpath=/opt/nfsroot\0" \
772"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
773 "sf probe 0; sf erase 0 +$filesize; " \
774 "sf write $loadaddr 0 $filesize\0" \
775"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
776 "protect off 0xeC000000 +$filesize; " \
777 "erase 0xEC000000 +$filesize; " \
778 "cp.b $loadaddr 0xEC000000 $filesize; " \
779 "cmp.b $loadaddr 0xEC000000 $filesize; " \
780 "protect on 0xeC000000 +$filesize\0" \
781"tftpflash=tftpboot $loadaddr $uboot; " \
782 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
783 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
784 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
785 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
786 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
787"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
788"ubootfile=u-boot.bin\0" \
789"upgrade=run flashuboot\0" \
790"usb_phy_type=ulpi\0 " \
791"boot_nfs= " \
792 "setenv bootargs root=/dev/nfs rw " \
793 "nfsroot=$serverip:$rootpath " \
794 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
795 "console=$consoledev,$baudrate $othbootargs;" \
796 "tftp $loadaddr $bootfile;" \
797 "tftp $fdtaddr $fdtfile;" \
798 "bootm $loadaddr - $fdtaddr\0" \
799"boot_hd = " \
800 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
801 "console=$consoledev,$baudrate $othbootargs;" \
802 "usb start;" \
803 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
804 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
805 "bootm $loadaddr - $fdtaddr\0" \
806"boot_usb_fat = " \
807 "setenv bootargs root=/dev/ram rw " \
808 "console=$consoledev,$baudrate $othbootargs " \
809 "ramdisk_size=$ramdisk_size;" \
810 "usb start;" \
811 "fatload usb 0:2 $loadaddr $bootfile;" \
812 "fatload usb 0:2 $fdtaddr $fdtfile;" \
813 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
814 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
815"boot_usb_ext2 = " \
816 "setenv bootargs root=/dev/ram rw " \
817 "console=$consoledev,$baudrate $othbootargs " \
818 "ramdisk_size=$ramdisk_size;" \
819 "usb start;" \
820 "ext2load usb 0:4 $loadaddr $bootfile;" \
821 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
822 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
823 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
824"boot_nor = " \
825 "setenv bootargs root=/dev/$jffs2nor rw " \
826 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
827 "bootm $norbootaddr - $norfdtaddr\0 " \
828"boot_ram = " \
829 "setenv bootargs root=/dev/ram rw " \
830 "console=$consoledev,$baudrate $othbootargs " \
831 "ramdisk_size=$ramdisk_size;" \
832 "tftp $ramdiskaddr $ramdiskfile;" \
833 "tftp $loadaddr $bootfile;" \
834 "tftp $fdtaddr $fdtfile;" \
835 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
836
837#endif
838#endif
839
840#endif
841