LXR uboot/include/configs/pcm058.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) Stefano Babic <sbabic@denx.de>
   4 */
   5
   6
   7#ifndef __PCM058_CONFIG_H
   8#define __PCM058_CONFIG_H
   9
  10#ifdef CONFIG_SPL
  11#define CONFIG_SYS_SPI_U_BOOT_OFFS      (64 * 1024)
  12#include "imx6_spl.h"
  13#endif
  14
  15#include "mx6_common.h"
  16
  17/* Thermal */
  18#define CONFIG_IMX_THERMAL
  19
  20/* Serial */
  21#define CONFIG_MXC_UART
  22#define CONFIG_MXC_UART_BASE           UART2_BASE
  23#define CONSOLE_DEV             "ttymxc1"
  24
  25#define PHYS_SDRAM_SIZE         (1u * 1024 * 1024 * 1024)
  26
  27/* Early setup */
  28
  29
  30/* Size of malloc() pool */
  31#define CONFIG_SYS_MALLOC_LEN           (8 * SZ_1M)
  32
  33/* Ethernet */
  34#define CONFIG_FEC_MXC
  35#define IMX_FEC_BASE                    ENET_BASE_ADDR
  36#define CONFIG_FEC_XCV_TYPE             RGMII
  37#define CONFIG_ETHPRIME                 "FEC"
  38#define CONFIG_FEC_MXC_PHYADDR          3
  39
  40/* SPI Flash */
  41#define CONFIG_SF_DEFAULT_BUS           0
  42#define CONFIG_SF_DEFAULT_CS            0
  43#define CONFIG_SF_DEFAULT_SPEED         20000000
  44#define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
  45
  46/* I2C Configs */
  47#define CONFIG_SYS_I2C
  48#define CONFIG_SYS_I2C_MXC
  49#define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 2 */
  50#define CONFIG_SYS_I2C_SPEED              100000
  51
  52#ifndef CONFIG_SPL_BUILD
  53/* Enable NAND support */
  54#define CONFIG_SYS_MAX_NAND_DEVICE      1
  55#define CONFIG_SYS_NAND_BASE            0x40000000
  56#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  57#define CONFIG_SYS_NAND_ONFI_DETECTION
  58#define CONFIG_SYS_NAND_USE_FLASH_BBT
  59#endif
  60
  61/* DMA stuff, needed for GPMI/MXS NAND support */
  62
  63/* Filesystem support */
  64
  65/* Physical Memory Map */
  66#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
  67
  68#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
  69#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
  70#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
  71
  72#define CONFIG_SYS_INIT_SP_OFFSET \
  73        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  74#define CONFIG_SYS_INIT_SP_ADDR \
  75        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  76
  77/* MMC Configs */
  78#define CONFIG_SYS_FSL_ESDHC_ADDR       0
  79#define CONFIG_SYS_FSL_USDHC_NUM        1
  80
  81/* Environment organization */
  82#define CONFIG_ENV_SIZE                (16 * 1024)
  83#define CONFIG_ENV_OFFSET               (1024 * SZ_1K)
  84#define CONFIG_ENV_SECT_SIZE            (64 * SZ_1K)
  85#define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
  86#define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
  87#define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
  88#define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
  89#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  90#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + \
  91                                                CONFIG_ENV_SECT_SIZE)
  92#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
  93
  94#ifdef CONFIG_ENV_IS_IN_NAND
  95#define CONFIG_ENV_OFFSET              (0x1E0000)
  96#define CONFIG_ENV_SECT_SIZE           (128 * SZ_1K)
  97#endif
  98
  99#endif
 100