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14#include <common.h>
15#include <asm/io.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/clocks_omap3.h>
18#include <asm/arch/mem.h>
19#include <asm/arch/sys_proto.h>
20#include <environment.h>
21#include <command.h>
22
23
24
25
26
27u32 get_osc_clk_speed(void)
28{
29 u32 start, cstart, cend, cdiff, cdiv, val;
30 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
31 struct prm *prm_base = (struct prm *)PRM_BASE;
32 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
33 struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
34
35 val = readl(&prm_base->clksrc_ctrl);
36
37 if (val & SYSCLKDIV_2)
38 cdiv = 2;
39 else
40 cdiv = 1;
41
42
43 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
44
45
46 writel(val, &prcm_base->clksel_wkup);
47
48
49 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
50 writel(val, &prcm_base->iclken_wkup);
51
52 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
53 writel(val, &prcm_base->fclken_wkup);
54
55 writel(0, &gpt1_base->tldr);
56 writel(GPT_EN, &gpt1_base->tclr);
57
58
59
60
61 start = 20 + readl(&s32k_base->s32k_cr);
62
63
64 while (readl(&s32k_base->s32k_cr) < start);
65
66
67 cstart = readl(&gpt1_base->tcrr);
68
69
70 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
71 cend = readl(&gpt1_base->tcrr);
72 cdiff = cend - cstart;
73 cdiff *= cdiv;
74
75
76 if (cdiff > 19000)
77 return S38_4M;
78 else if (cdiff > 15200)
79 return S26M;
80 else if (cdiff > 13000)
81 return S24M;
82 else if (cdiff > 9000)
83 return S19_2M;
84 else if (cdiff > 7600)
85 return S13M;
86 else
87 return S12M;
88}
89
90
91
92
93
94void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
95{
96 switch(osc_clk) {
97 case S38_4M:
98 *sys_clkin_sel = 4;
99 break;
100 case S26M:
101 *sys_clkin_sel = 3;
102 break;
103 case S19_2M:
104 *sys_clkin_sel = 2;
105 break;
106 case S13M:
107 *sys_clkin_sel = 1;
108 break;
109 case S12M:
110 default:
111 *sys_clkin_sel = 0;
112 }
113}
114
115
116
117
118
119static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
120{
121 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
122 dpll_param *ptr = (dpll_param *) get_core_dpll_param();
123 void (*f_lock_pll) (u32, u32, u32, u32);
124 int xip_safe, p0, p1, p2, p3;
125
126 xip_safe = is_running_in_sram();
127
128
129 ptr = ptr + (3 * clk_index) + sil_index;
130
131 if (xip_safe) {
132
133
134
135 clrsetbits_le32(&prcm_base->clken_pll,
136 0x00000007, PLL_FAST_RELOCK_BYPASS);
137 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
138 LDELAY);
139
140
141
142
143
144
145
146 clrsetbits_le32(&prcm_base->clksel1_emu,
147 0x001F0000, (CORE_M3X2 + 1) << 16) ;
148 clrsetbits_le32(&prcm_base->clksel1_emu,
149 0x001F0000, CORE_M3X2 << 16);
150
151
152 clrsetbits_le32(&prcm_base->clksel1_pll,
153 0xF8000000, ptr->m2 << 27);
154
155
156 clrsetbits_le32(&prcm_base->clksel1_pll,
157 0x07FF0000, ptr->m << 16);
158
159
160 clrsetbits_le32(&prcm_base->clksel1_pll,
161 0x00007F00, ptr->n << 8);
162
163
164 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
165
166
167 clrsetbits_le32(&prcm_base->clksel_core,
168 0x00000F00, CORE_SSI_DIV << 8);
169
170 clrsetbits_le32(&prcm_base->clksel_core,
171 0x00000030, CORE_FUSB_DIV << 4);
172
173 clrsetbits_le32(&prcm_base->clksel_core,
174 0x0000000C, CORE_L4_DIV << 2);
175
176 clrsetbits_le32(&prcm_base->clksel_core,
177 0x00000003, CORE_L3_DIV);
178
179 clrsetbits_le32(&prcm_base->clksel_gfx,
180 0x00000007, GFX_DIV);
181
182 clrsetbits_le32(&prcm_base->clksel_wkup,
183 0x00000006, WKUP_RSM << 1);
184
185 clrsetbits_le32(&prcm_base->clken_pll,
186 0x000000F0, ptr->fsel << 4);
187
188 clrsetbits_le32(&prcm_base->clken_pll,
189 0x00000007, PLL_LOCK);
190
191 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
192 LDELAY);
193 } else if (is_running_in_flash()) {
194
195
196
197
198 f_lock_pll = (void *) (SRAM_CLK_CODE);
199
200 p0 = readl(&prcm_base->clken_pll);
201 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
202
203 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
204
205 p1 = readl(&prcm_base->clksel1_pll);
206
207 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
208
209 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
210
211 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
212
213 clrbits_le32(&p1, 0x00000040);
214
215 p2 = readl(&prcm_base->clksel_core);
216
217 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
218
219 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
220
221 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
222
223 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
224
225 p3 = (u32)&prcm_base->idlest_ckgen;
226
227 (*f_lock_pll) (p0, p1, p2, p3);
228 }
229}
230
231static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
232{
233 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
234 dpll_param *ptr = (dpll_param *) get_per_dpll_param();
235
236
237 ptr = ptr + clk_index;
238
239
240 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
241 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
242
243
244
245
246
247
248
249 clrsetbits_le32(&prcm_base->clksel1_emu,
250 0x1F000000, (PER_M6X2 + 1) << 24);
251 clrsetbits_le32(&prcm_base->clksel1_emu,
252 0x1F000000, PER_M6X2 << 24);
253
254 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
255 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
256
257 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
258 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
259
260 clrsetbits_le32(&prcm_base->clksel_dss,
261 0x00001F00, (PER_M3X2 + 1) << 8);
262 clrsetbits_le32(&prcm_base->clksel_dss,
263 0x00001F00, PER_M3X2 << 8);
264
265 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
266 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
267
268
269
270 clrsetbits_le32(&prcm_base->clksel2_pll,
271 0x0007FF00, ptr->m << 8);
272
273
274 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
275
276
277 clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
278
279
280 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
281 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
282}
283
284static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
285{
286 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
287 dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
288
289
290 ptr = ptr + clk_index;
291
292
293 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
294 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
295
296 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
297
298 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
299
300 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
301
302 clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
303
304 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
305 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
306}
307
308static void mpu_init_34xx(u32 sil_index, u32 clk_index)
309{
310 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
311 dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
312
313
314 ptr = ptr + (3 * clk_index) + sil_index;
315
316
317
318
319 clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
320 0x0000001F, ptr->m2);
321
322
323 clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
324 0x0007FF00, ptr->m << 8);
325
326
327 clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
328 0x0000007F, ptr->n);
329
330
331 clrsetbits_le32(&prcm_base->clken_pll_mpu,
332 0x000000F0, ptr->fsel << 4);
333}
334
335static void iva_init_34xx(u32 sil_index, u32 clk_index)
336{
337 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
338 dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
339
340
341 ptr = ptr + (3 * clk_index) + sil_index;
342
343
344
345 clrsetbits_le32(&prcm_base->clken_pll_iva2,
346 0x00000007, PLL_STOP);
347 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
348
349
350 clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
351 0x0000001F, ptr->m2);
352
353
354 clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
355 0x0007FF00, ptr->m << 8);
356
357
358 clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
359 0x0000007F, ptr->n);
360
361
362 clrsetbits_le32(&prcm_base->clken_pll_iva2,
363 0x000000F0, ptr->fsel << 4);
364
365
366 clrsetbits_le32(&prcm_base->clken_pll_iva2,
367 0x00000007, PLL_LOCK);
368
369 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
370}
371
372
373
374
375
376static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
377{
378 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
379 dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
380 void (*f_lock_pll) (u32, u32, u32, u32);
381 int xip_safe, p0, p1, p2, p3;
382
383 xip_safe = is_running_in_sram();
384
385
386 ptr += clk_index;
387
388 if (xip_safe) {
389
390
391
392 clrsetbits_le32(&prcm_base->clken_pll,
393 0x00000007, PLL_FAST_RELOCK_BYPASS);
394 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
395 LDELAY);
396
397
398 clrsetbits_le32(&prcm_base->clksel1_emu,
399 0x001F0000, CORE_M3X2 << 16);
400
401
402 clrsetbits_le32(&prcm_base->clksel1_pll,
403 0xF8000000, ptr->m2 << 27);
404
405
406 clrsetbits_le32(&prcm_base->clksel1_pll,
407 0x07FF0000, ptr->m << 16);
408
409
410 clrsetbits_le32(&prcm_base->clksel1_pll,
411 0x00007F00, ptr->n << 8);
412
413
414 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
415
416
417 clrsetbits_le32(&prcm_base->clksel_core,
418 0x00000F00, CORE_SSI_DIV << 8);
419
420 clrsetbits_le32(&prcm_base->clksel_core,
421 0x00000030, CORE_FUSB_DIV << 4);
422
423 clrsetbits_le32(&prcm_base->clksel_core,
424 0x0000000C, CORE_L4_DIV << 2);
425
426 clrsetbits_le32(&prcm_base->clksel_core,
427 0x00000003, CORE_L3_DIV);
428
429 clrsetbits_le32(&prcm_base->clksel_gfx,
430 0x00000007, GFX_DIV_36X);
431
432 clrsetbits_le32(&prcm_base->clksel_wkup,
433 0x00000006, WKUP_RSM << 1);
434
435 clrsetbits_le32(&prcm_base->clken_pll,
436 0x000000F0, ptr->fsel << 4);
437
438 clrsetbits_le32(&prcm_base->clken_pll,
439 0x00000007, PLL_LOCK);
440
441 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
442 LDELAY);
443 } else if (is_running_in_flash()) {
444
445
446
447
448 f_lock_pll = (void *) (SRAM_CLK_CODE);
449
450 p0 = readl(&prcm_base->clken_pll);
451 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
452
453 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
454
455 p1 = readl(&prcm_base->clksel1_pll);
456
457 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
458
459 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
460
461 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
462
463 clrbits_le32(&p1, 0x00000040);
464
465 p2 = readl(&prcm_base->clksel_core);
466
467 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
468
469 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
470
471 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
472
473 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
474
475 p3 = (u32)&prcm_base->idlest_ckgen;
476
477 (*f_lock_pll) (p0, p1, p2, p3);
478 }
479}
480
481static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
482{
483 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
484 struct dpll_per_36x_param *ptr;
485
486 ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
487
488
489 ptr += clk_index;
490
491
492 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
493 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
494
495
496 clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
497
498
499 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
500
501
502 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
503
504
505 clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
506
507
508 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
509
510
511 clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
512
513
514 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
515
516
517 clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
518
519
520 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
521 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
522}
523
524static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
525{
526 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
527 dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
528
529
530 ptr = ptr + clk_index;
531
532
533 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
534 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
535
536 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
537
538 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
539
540 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
541
542 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
543 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
544}
545
546static void mpu_init_36xx(u32 sil_index, u32 clk_index)
547{
548 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
549 dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
550
551
552 ptr += clk_index;
553
554
555
556
557 clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
558
559
560 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
561
562
563 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
564}
565
566static void iva_init_36xx(u32 sil_index, u32 clk_index)
567{
568 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
569 dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
570
571
572 ptr += clk_index;
573
574
575
576 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
577 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
578
579
580 clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
581
582
583 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
584
585
586 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
587
588
589 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
590
591 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
592}
593
594
595
596
597
598void prcm_init(void)
599{
600 u32 osc_clk = 0, sys_clkin_sel;
601 u32 clk_index, sil_index = 0;
602 struct prm *prm_base = (struct prm *)PRM_BASE;
603 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
604
605
606
607
608
609 osc_clk = get_osc_clk_speed();
610 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
611
612
613 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
614
615
616 if (sys_clkin_sel > 2) {
617
618 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
619 clk_index = sys_clkin_sel / 2;
620 } else {
621
622 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
623 clk_index = sys_clkin_sel;
624 }
625
626 if (get_cpu_family() == CPU_OMAP36XX) {
627
628
629
630
631
632
633
634
635
636
637
638
639 if (sys_clkin_sel != 1) {
640
641 clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
642 }
643
644
645 clrsetbits_le32(&prcm_base->clken_pll_mpu,
646 0x00000007, PLL_LOW_POWER_BYPASS);
647 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
648 LDELAY);
649
650 dpll3_init_36xx(0, clk_index);
651 dpll4_init_36xx(0, clk_index);
652 dpll5_init_36xx(0, clk_index);
653 iva_init_36xx(0, clk_index);
654 mpu_init_36xx(0, clk_index);
655
656
657 clrsetbits_le32(&prcm_base->clken_pll_mpu,
658 0x00000007, PLL_LOCK);
659 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
660 LDELAY);
661 } else {
662
663
664
665
666
667
668
669 if (((get_cpu_family() == CPU_OMAP34XX)
670 && (get_cpu_rev() >= CPU_3XX_ES20)) ||
671 (get_cpu_family() == CPU_AM35XX))
672 sil_index = 1;
673
674
675 clrsetbits_le32(&prcm_base->clken_pll_mpu,
676 0x00000007, PLL_LOW_POWER_BYPASS);
677 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
678 LDELAY);
679
680 dpll3_init_34xx(sil_index, clk_index);
681 dpll4_init_34xx(sil_index, clk_index);
682 dpll5_init_34xx(sil_index, clk_index);
683 if (get_cpu_family() != CPU_AM35XX)
684 iva_init_34xx(sil_index, clk_index);
685
686 mpu_init_34xx(sil_index, clk_index);
687
688
689 clrsetbits_le32(&prcm_base->clken_pll_mpu,
690 0x00000007, PLL_LOCK);
691 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
692 LDELAY);
693 }
694
695
696 setbits_le32(&prcm_base->clksel_per, 0x000000FF);
697 setbits_le32(&prcm_base->clksel_wkup, 1);
698
699 sdelay(5000);
700}
701
702
703
704
705void ehci_clocks_enable(void)
706{
707 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
708
709
710 setbits_le32(&prcm_base->iclken_usbhost, 1);
711
712
713
714
715 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
716
717 setbits_le32(&prcm_base->iclken3_core, 0x00000004);
718
719 setbits_le32(&prcm_base->fclken3_core, 0x00000004);
720}
721
722
723
724
725void per_clocks_enable(void)
726{
727 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
728
729
730 setbits_le32(&prcm_base->clksel_per, 0x01);
731 setbits_le32(&prcm_base->iclken_per, 0x08);
732 setbits_le32(&prcm_base->fclken_per, 0x08);
733
734
735 setbits_le32(&prcm_base->clksel_per, 0x80);
736 setbits_le32(&prcm_base->iclken_per, 0x400);
737 setbits_le32(&prcm_base->fclken_per, 0x400);
738
739#ifdef CONFIG_SYS_NS16550
740
741 setbits_le32(&prcm_base->fclken1_core, 0x00002000);
742 setbits_le32(&prcm_base->iclken1_core, 0x00002000);
743
744
745 setbits_le32(&prcm_base->fclken1_core, 0x00004000);
746 setbits_le32(&prcm_base->iclken1_core, 0x00004000);
747
748
749 setbits_le32(&prcm_base->fclken_per, 0x00000800);
750 setbits_le32(&prcm_base->iclken_per, 0x00000800);
751#endif
752
753#if defined(CONFIG_OMAP3_GPIO_2)
754 setbits_le32(&prcm_base->fclken_per, 0x00002000);
755 setbits_le32(&prcm_base->iclken_per, 0x00002000);
756#endif
757#if defined(CONFIG_OMAP3_GPIO_3)
758 setbits_le32(&prcm_base->fclken_per, 0x00004000);
759 setbits_le32(&prcm_base->iclken_per, 0x00004000);
760#endif
761#if defined(CONFIG_OMAP3_GPIO_4)
762 setbits_le32(&prcm_base->fclken_per, 0x00008000);
763 setbits_le32(&prcm_base->iclken_per, 0x00008000);
764#endif
765#if defined(CONFIG_OMAP3_GPIO_5)
766 setbits_le32(&prcm_base->fclken_per, 0x00010000);
767 setbits_le32(&prcm_base->iclken_per, 0x00010000);
768#endif
769#if defined(CONFIG_OMAP3_GPIO_6)
770 setbits_le32(&prcm_base->fclken_per, 0x00020000);
771 setbits_le32(&prcm_base->iclken_per, 0x00020000);
772#endif
773
774#ifdef CONFIG_SYS_I2C_OMAP24XX
775
776 setbits_le32(&prcm_base->fclken1_core, 0x00038000);
777 setbits_le32(&prcm_base->iclken1_core, 0x00038000);
778#endif
779
780 setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
781
782 if (get_cpu_family() != CPU_AM35XX)
783 out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
784
785 out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
786 out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
787 out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
788 out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
789 out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
790 out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
791 out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
792 if (get_cpu_family() != CPU_AM35XX) {
793 out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
794 out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
795 }
796
797 sdelay(1000);
798}
799