1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7#ifndef _ASM_ARCH_HARDWARE_H 8#define _ASM_ARCH_HARDWARE_H 9 10#define ARASAN_NAND_BASEADDR 0xFF100000 11 12#define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 13#define ZYNQMP_TCM_SIZE 0x40000 14 15#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 16#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 17#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 18#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 19 20#define PS_MODE0 BIT(0) 21#define PS_MODE1 BIT(1) 22#define PS_MODE2 BIT(2) 23#define PS_MODE3 BIT(3) 24 25#define RESET_REASON_DEBUG_SYS BIT(6) 26#define RESET_REASON_SOFT BIT(5) 27#define RESET_REASON_SRST BIT(4) 28#define RESET_REASON_PSONLY BIT(3) 29#define RESET_REASON_PMU BIT(2) 30#define RESET_REASON_INTERNAL BIT(1) 31#define RESET_REASON_EXTERNAL BIT(0) 32 33struct crlapb_regs { 34 u32 reserved0[36]; 35 u32 cpu_r5_ctrl; /* 0x90 */ 36 u32 reserved1[37]; 37 u32 timestamp_ref_ctrl; /* 0x128 */ 38 u32 reserved2[53]; 39 u32 boot_mode; /* 0x200 */ 40 u32 reserved3_0[7]; 41 u32 reset_reason; /* 0x220 */ 42 u32 reserved3_1[6]; 43 u32 rst_lpd_top; /* 0x23C */ 44 u32 reserved4[4]; 45 u32 boot_pin_ctrl; /* 0x250 */ 46 u32 reserved5[21]; 47}; 48 49#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 50 51#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 52#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 53#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 54 55struct iou_scntr_secure { 56 u32 counter_control_register; 57 u32 reserved0[7]; 58 u32 base_frequency_id_register; 59}; 60 61#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 62 63/* Bootmode setting values */ 64#define BOOT_MODES_MASK 0x0000000F 65#define QSPI_MODE_24BIT 0x00000001 66#define QSPI_MODE_32BIT 0x00000002 67#define SD_MODE 0x00000003 /* sd 0 */ 68#define SD_MODE1 0x00000005 /* sd 1 */ 69#define NAND_MODE 0x00000004 70#define EMMC_MODE 0x00000006 71#define USB_MODE 0x00000007 72#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 73#define JTAG_MODE 0x00000000 74#define BOOT_MODE_USE_ALT 0x100 75#define BOOT_MODE_ALT_SHIFT 12 76/* SW secondary boot modes 0xa - 0xd */ 77#define SW_USBHOST_MODE 0x0000000A 78#define SW_SATA_MODE 0x0000000B 79 80#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 81 82struct iou_slcr_regs { 83 u32 mio_pin[78]; 84 u32 reserved[442]; 85}; 86 87#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 88 89#define ZYNQMP_RPU_BASEADDR 0xFF9A0000 90 91struct rpu_regs { 92 u32 rpu_glbl_ctrl; 93 u32 reserved0[63]; 94 u32 rpu0_cfg; /* 0x100 */ 95 u32 reserved1[63]; 96 u32 rpu1_cfg; /* 0x200 */ 97}; 98 99#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 100 101#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 102 103struct crfapb_regs { 104 u32 reserved0[65]; 105 u32 rst_fpd_apu; /* 0x104 */ 106 u32 reserved1; 107}; 108 109#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 110 111#define ZYNQMP_APU_BASEADDR 0xFD5C0000 112 113struct apu_regs { 114 u32 reserved0[16]; 115 u32 rvbar_addr0_l; /* 0x40 */ 116 u32 rvbar_addr0_h; /* 0x44 */ 117 u32 reserved1[20]; 118}; 119 120#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 121 122/* Board version value */ 123#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 124#define ZYNQMP_CSU_VERSION_SILICON 0x0 125#define ZYNQMP_CSU_VERSION_QEMU 0x3 126 127#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 128 129#define ZYNQMP_SILICON_VER_MASK 0xF000 130#define ZYNQMP_SILICON_VER_SHIFT 12 131 132struct csu_regs { 133 u32 reserved0[17]; 134 u32 version; 135}; 136 137#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 138 139#define ZYNQMP_PMU_BASEADDR 0xFFD80000 140 141struct pmu_regs { 142 u32 reserved[18]; 143 u32 gen_storage6; /* 0x48 */ 144}; 145 146#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) 147 148#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 149#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 150 151#endif /* _ASM_ARCH_HARDWARE_H */ 152