1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2011, Google Inc. 4 */ 5 6#ifndef ASM_ARCH_PEI_DATA_H 7#define ASM_ARCH_PEI_DATA_H 8 9#include <linux/linkage.h> 10 11struct pch_usb3_controller_settings { 12 /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ 13 uint16_t mode; 14 /* 4 bit mask, 1: switchable, 0: not switchable */ 15 uint16_t hs_port_switch_mask; 16 /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ 17 uint16_t preboot_support; 18 /* 0: Disable, 1: Enable */ 19 uint16_t xhci_streams; 20}; 21 22typedef asmlinkage void (*tx_byte_func)(unsigned char byte); 23 24#define PEI_VERSION 6 25 26struct __packed pei_data { 27 uint32_t pei_version; 28 uint32_t mchbar; 29 uint32_t dmibar; 30 uint32_t epbar; 31 uint32_t pciexbar; 32 uint16_t smbusbar; 33 uint32_t wdbbar; 34 uint32_t wdbsize; 35 uint32_t hpet_address; 36 uint32_t rcba; 37 uint32_t pmbase; 38 uint32_t gpiobase; 39 uint32_t thermalbase; 40 uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ 41 uint32_t tseg_size; 42 uint8_t spd_addresses[4]; 43 uint8_t ts_addresses[4]; 44 int boot_mode; 45 int ec_present; 46 int gbe_enable; 47 /* 48 * 0 = leave channel enabled 49 * 1 = disable dimm 0 on channel 50 * 2 = disable dimm 1 on channel 51 * 3 = disable dimm 0+1 on channel 52 */ 53 int dimm_channel0_disabled; 54 int dimm_channel1_disabled; 55 /* Seed values saved in CMOS */ 56 uint32_t scrambler_seed; 57 uint32_t scrambler_seed_s3; 58 /* Data read from flash and passed into MRC */ 59 unsigned char *mrc_input; 60 unsigned int mrc_input_len; 61 /* Data from MRC that should be saved to flash */ 62 unsigned char *mrc_output; 63 unsigned int mrc_output_len; 64 /* 65 * Max frequency DDR3 could be ran at. Could be one of four values: 66 * 800, 1067, 1333, 1600 67 */ 68 uint32_t max_ddr3_freq; 69 /* 70 * USB Port Configuration: 71 * [0] = enable 72 * [1] = overcurrent pin 73 * [2] = length 74 * 75 * Ports 0-7 can be mapped to OC0-OC3 76 * Ports 8-13 can be mapped to OC4-OC7 77 * 78 * Port Length 79 * MOBILE: 80 * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) 81 * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) 82 * DESKTOP: 83 * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) 84 * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) 85 * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) 86 */ 87 uint16_t usb_port_config[16][3]; 88 /* See the usb3 struct above for details */ 89 struct pch_usb3_controller_settings usb3; 90 /* 91 * SPD data array for onboard RAM. Specify address 0xf0, 92 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in 93 * spd_address for a given "DIMM". 94 */ 95 uint8_t spd_data[4][256]; 96 tx_byte_func tx_byte; 97 int ddr3lv_support; 98 /* 99 * pcie_init needs to be set to 1 to have the system agent initialise 100 * PCIe. Note: This should only be required if your system has Gen3 101 * devices and it will increase your boot time by at least 100ms. 102 */ 103 int pcie_init; 104 /* 105 * N mode functionality. Leave this setting at 0. 106 * 0 Auto 107 * 1 1N 108 * 2 2N 109 */ 110 int nmode; 111 /* 112 * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows 113 * for DIMM SPD data to specify whether double-rate is required for 114 * extended operating temperature range. 115 * 0 Enable double rate based upon temperature thresholds 116 * 1 Normal rate 117 * 2 Always enable double rate 118 */ 119 int ddr_refresh_rate_config; 120}; 121 122#endif 123