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9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
14#include <asm/arch/mx6-pins.h>
15#include <asm/gpio.h>
16#include <asm/mach-imx/iomux-v3.h>
17#include <asm/mach-imx/sata.h>
18#include <asm/mach-imx/boot_mode.h>
19#include <asm/mach-imx/mxc_i2c.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/arch/mxc_hdmi.h>
22#include <asm/arch/crm_regs.h>
23#include <mmc.h>
24#include <fsl_esdhc.h>
25#include <i2c.h>
26#include <input.h>
27#include <power/pmic.h>
28#include <power/pfuze100_pmic.h>
29#include <linux/fb.h>
30#include <ipu_pixfmt.h>
31#include <malloc.h>
32#include <miiphy.h>
33#include <netdev.h>
34#include <micrel.h>
35#include <spi_flash.h>
36#include <spi.h>
37
38DECLARE_GLOBAL_DATA_PTR;
39
40#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
41 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50
51#define SPI_PAD_CTRL (PAD_CTL_HYS | \
52 PAD_CTL_SPEED_MED | \
53 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
54
55#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
56
57
58#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
61
62int dram_init(void)
63{
64 gd->ram_size = imx_ddr_size();
65
66 return 0;
67}
68
69static iomux_v3_cfg_t const uart2_pads[] = {
70 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
71 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
72};
73
74#ifndef CONFIG_SPL_BUILD
75static iomux_v3_cfg_t const usdhc2_pads[] = {
76 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
79 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
80 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
81 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
82 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
83};
84
85static iomux_v3_cfg_t const usdhc3_pads[] = {
86 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
89 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
90 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
91 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
92 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
93 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
94 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
95 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
96 IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
97};
98#endif
99
100static iomux_v3_cfg_t const usdhc4_pads[] = {
101 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
102 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
103 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
104 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
105 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
106 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
107 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
108 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
109 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
110 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
111 IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112};
113
114static iomux_v3_cfg_t const usb_otg_pads[] = {
115 IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
116 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
117};
118
119static iomux_v3_cfg_t enet_pads_ksz9031[] = {
120 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
121 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
122 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
123 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
124 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
125 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
126 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
127 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
128 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
129 IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
130 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
131 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
132 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
133 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
134 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
135};
136
137static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
138 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
139 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
140 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
141 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
142 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
143 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
144};
145
146static iomux_v3_cfg_t enet_pads_ar8035[] = {
147 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
148 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
149 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
150 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
151 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
152 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
153 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
154 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
155 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
156 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
157 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
158 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
159 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
160 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
161 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
162};
163
164static iomux_v3_cfg_t const ecspi1_pads[] = {
165 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
166 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
167 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
168 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
169};
170
171#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
172struct i2c_pads_info mx6q_i2c_pad_info1 = {
173 .scl = {
174 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
175 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
176 .gp = IMX_GPIO_NR(4, 12)
177 },
178 .sda = {
179 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
180 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
181 .gp = IMX_GPIO_NR(4, 13)
182 }
183};
184
185struct i2c_pads_info mx6dl_i2c_pad_info1 = {
186 .scl = {
187 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
188 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
189 .gp = IMX_GPIO_NR(4, 12)
190 },
191 .sda = {
192 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
193 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
194 .gp = IMX_GPIO_NR(4, 13)
195 }
196};
197
198#define I2C_PMIC 1
199
200struct interface_level {
201 char *name;
202 uchar value;
203};
204
205static struct interface_level mipi_levels[] = {
206 {"0V0", 0x00},
207 {"2V5", 0x17},
208};
209
210
211int power_init_board(void)
212{
213 struct pmic *p;
214 u32 id1, id2, i;
215 int ret;
216 char const *lv_mipi;
217
218
219 gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
220
221 power_pfuze100_init(I2C_PMIC);
222 p = pmic_get("PFUZE100");
223 if (!p)
224 return -EINVAL;
225
226 ret = pmic_probe(p);
227 if (ret)
228 return ret;
229
230 pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
231 pmic_reg_read(p, PFUZE100_REVID, &id2);
232 printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
233
234 if (id2 >= 0x20)
235 return 0;
236
237
238 lv_mipi = env_get("lv_mipi");
239 if (lv_mipi)
240 return 0;
241
242 for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
243 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
244 printf("set MIPI level %s\n", mipi_levels[i].name);
245 ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
246 mipi_levels[i].value);
247 if (ret)
248 return ret;
249 }
250 }
251
252 return 0;
253}
254
255int board_eth_init(bd_t *bis)
256{
257 struct phy_device *phydev;
258 struct mii_dev *bus;
259 unsigned short id1, id2;
260 int ret;
261
262
263 SETUP_IOMUX_PADS(enet_pads_ar8035);
264
265
266 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
267 udelay(2000);
268 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
269 udelay(500);
270
271 bus = fec_get_miibus(IMX_FEC_BASE, -1);
272 if (!bus)
273 return -EINVAL;
274 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
275 if (!phydev) {
276 printf("Error: phy device not found.\n");
277 ret = -ENODEV;
278 goto free_bus;
279 }
280
281
282 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
283 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
284
285 if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
286
287 printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
288 phydev->addr);
289
290
291 gpio_set_value(IMX_GPIO_NR(3, 23), 0);
292 gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
293 gpio_set_value(IMX_GPIO_NR(6, 25), 1);
294 gpio_set_value(IMX_GPIO_NR(6, 27), 1);
295 gpio_set_value(IMX_GPIO_NR(6, 28), 1);
296 gpio_set_value(IMX_GPIO_NR(6, 29), 1);
297 SETUP_IOMUX_PADS(enet_pads_ksz9031);
298 gpio_set_value(IMX_GPIO_NR(6, 24), 1);
299 udelay(500);
300 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
301 SETUP_IOMUX_PADS(enet_pads_final_ksz9031);
302 } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
303
304 printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
305 phydev->addr);
306 } else {
307 printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
308 ret = -EINVAL;
309 goto free_phydev;
310 }
311
312 ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
313 if (ret)
314 goto free_phydev;
315
316 return 0;
317
318free_phydev:
319 free(phydev);
320free_bus:
321 free(bus);
322 return ret;
323}
324
325int mx6_rgmii_rework(struct phy_device *phydev)
326{
327 unsigned short id1, id2;
328 unsigned short val;
329
330
331 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
332 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
333
334 if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
335
336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
338 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
339 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
340
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
343 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
344 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
345
346 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
347 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
348 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
349 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
350
351 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
352 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
353 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
354 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
355
356
357 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
358 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
359 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
360 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
361 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
362 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
363 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
364 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
365 }
366
367 if ((id1 == 0x004d) && (id2 == 0xd072)) {
368
369 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
370 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
371 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
372 val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
373 val &= 0xfe63;
374 val |= 0x18;
375 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
376
377
378 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
379 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
380 val |= 0x0100;
381 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
382
383
384 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
385 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
386 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
387 }
388 return 0;
389}
390
391int board_phy_config(struct phy_device *phydev)
392{
393 mx6_rgmii_rework(phydev);
394
395 if (phydev->drv->config)
396 phydev->drv->config(phydev);
397
398 return 0;
399}
400
401static void setup_iomux_uart(void)
402{
403 SETUP_IOMUX_PADS(uart2_pads);
404}
405
406#ifdef CONFIG_MXC_SPI
407static void setup_spi(void)
408{
409 SETUP_IOMUX_PADS(ecspi1_pads);
410 gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
411}
412#endif
413
414#ifdef CONFIG_FSL_ESDHC
415static struct fsl_esdhc_cfg usdhc_cfg[] = {
416 {USDHC2_BASE_ADDR},
417 {USDHC3_BASE_ADDR},
418 {USDHC4_BASE_ADDR},
419};
420
421int board_mmc_getcd(struct mmc *mmc)
422{
423 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
424 int ret = 0;
425
426 switch (cfg->esdhc_base) {
427 case USDHC2_BASE_ADDR:
428 gpio_direction_input(IMX_GPIO_NR(1, 4));
429 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
430 break;
431 case USDHC3_BASE_ADDR:
432 ret = 1;
433 break;
434 case USDHC4_BASE_ADDR:
435 gpio_direction_input(IMX_GPIO_NR(2, 6));
436 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
437 break;
438 default:
439 printf("Bad USDHC interface\n");
440 }
441
442 return ret;
443}
444
445int board_mmc_init(bd_t *bis)
446{
447#ifndef CONFIG_SPL_BUILD
448 s32 status = 0;
449 int i;
450
451 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
452 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
453 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
454
455 SETUP_IOMUX_PADS(usdhc2_pads);
456 SETUP_IOMUX_PADS(usdhc3_pads);
457 SETUP_IOMUX_PADS(usdhc4_pads);
458
459 for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
460 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
461 if (status)
462 return status;
463 }
464
465 return 0;
466#else
467 SETUP_IOMUX_PADS(usdhc4_pads);
468 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
469 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
470 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
471
472 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
473#endif
474}
475#endif
476
477int board_ehci_hcd_init(int port)
478{
479 switch (port) {
480 case 0:
481 SETUP_IOMUX_PADS(usb_otg_pads);
482
483
484
485
486 imx_iomux_set_gpr_register(1, 13, 1, 1);
487 break;
488 case 1:
489
490 break;
491 default:
492 printf("Invalid USB port: %d\n", port);
493 return -EINVAL;
494 }
495
496 return 0;
497}
498
499int board_ehci_power(int port, int on)
500{
501 switch (port) {
502 case 0:
503 break;
504 case 1:
505 gpio_direction_output(IMX_GPIO_NR(5, 5), on);
506 break;
507 default:
508 printf("Invalid USB port: %d\n", port);
509 return -EINVAL;
510 }
511
512 return 0;
513}
514
515struct display_info_t {
516 int bus;
517 int addr;
518 int pixfmt;
519 int (*detect)(struct display_info_t const *dev);
520 void (*enable)(struct display_info_t const *dev);
521 struct fb_videomode mode;
522};
523
524static void disable_lvds(struct display_info_t const *dev)
525{
526 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
527
528 clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
529 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
530}
531
532static void do_enable_hdmi(struct display_info_t const *dev)
533{
534 disable_lvds(dev);
535 imx_enable_hdmi_phy();
536}
537
538static struct display_info_t const displays[] = {
539{
540 .bus = -1,
541 .addr = 0,
542 .pixfmt = IPU_PIX_FMT_RGB666,
543 .detect = NULL,
544 .enable = NULL,
545 .mode = {
546 .name =
547 "Hannstar-XGA",
548 .refresh = 60,
549 .xres = 1024,
550 .yres = 768,
551 .pixclock = 15385,
552 .left_margin = 220,
553 .right_margin = 40,
554 .upper_margin = 21,
555 .lower_margin = 7,
556 .hsync_len = 60,
557 .vsync_len = 10,
558 .sync = FB_SYNC_EXT,
559 .vmode = FB_VMODE_NONINTERLACED } },
560{
561 .bus = -1,
562 .addr = 0,
563 .pixfmt = IPU_PIX_FMT_RGB24,
564 .detect = NULL,
565 .enable = do_enable_hdmi,
566 .mode = {
567 .name = "HDMI",
568 .refresh = 60,
569 .xres = 1024,
570 .yres = 768,
571 .pixclock = 15385,
572 .left_margin = 220,
573 .right_margin = 40,
574 .upper_margin = 21,
575 .lower_margin = 7,
576 .hsync_len = 60,
577 .vsync_len = 10,
578 .sync = FB_SYNC_EXT,
579 .vmode = FB_VMODE_NONINTERLACED } }
580};
581
582int board_video_skip(void)
583{
584 int i;
585 int ret;
586 char const *panel = env_get("panel");
587 if (!panel) {
588 for (i = 0; i < ARRAY_SIZE(displays); i++) {
589 struct display_info_t const *dev = displays + i;
590 if (dev->detect && dev->detect(dev)) {
591 panel = dev->mode.name;
592 printf("auto-detected panel %s\n", panel);
593 break;
594 }
595 }
596 if (!panel) {
597 panel = displays[0].mode.name;
598 printf("No panel detected: default to %s\n", panel);
599 i = 0;
600 }
601 } else {
602 for (i = 0; i < ARRAY_SIZE(displays); i++) {
603 if (!strcmp(panel, displays[i].mode.name))
604 break;
605 }
606 }
607 if (i < ARRAY_SIZE(displays)) {
608 ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
609 if (!ret) {
610 if (displays[i].enable)
611 displays[i].enable(displays + i);
612 printf("Display: %s (%ux%u)\n",
613 displays[i].mode.name, displays[i].mode.xres,
614 displays[i].mode.yres);
615 } else
616 printf("LCD %s cannot be configured: %d\n",
617 displays[i].mode.name, ret);
618 } else {
619 printf("unsupported panel %s\n", panel);
620 return -EINVAL;
621 }
622
623 return 0;
624}
625
626static void setup_display(void)
627{
628 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
629 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
630 int reg;
631
632 enable_ipu_clock();
633 imx_setup_hdmi();
634
635
636 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
637 MXC_CCM_CCGR3_LDB_DI1_MASK);
638
639
640 reg = readl(&mxc_ccm->cs2cdr);
641 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
642 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
643 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
644 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
645 writel(reg, &mxc_ccm->cs2cdr);
646
647 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
648 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
649
650 setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
651 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
652 CHSCCDR_CLK_SEL_LDB_DI0 <<
653 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
654
655 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
656 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
657 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
658 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
659 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
660 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
661 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
662 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
663 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
664 writel(reg, &iomux->gpr[2]);
665
666 reg = readl(&iomux->gpr[3]);
667 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
668 IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
669 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
670 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
671 writel(reg, &iomux->gpr[3]);
672}
673
674
675
676
677
678int overwrite_console(void)
679{
680 return 1;
681}
682
683int board_early_init_f(void)
684{
685 setup_iomux_uart();
686#ifdef CONFIG_MXC_SPI
687 setup_spi();
688#endif
689 return 0;
690}
691
692int board_init(void)
693{
694
695 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
696
697
698 if (is_mx6dq())
699 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
700 else
701 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
702
703 setup_display();
704
705#ifdef CONFIG_SATA
706 setup_sata();
707#endif
708
709 return 0;
710}
711
712int checkboard(void)
713{
714 char *type = "unknown";
715
716 if (is_cpu_type(MXC_CPU_MX6Q))
717 type = "Quad";
718 else if (is_cpu_type(MXC_CPU_MX6D))
719 type = "Dual";
720 else if (is_cpu_type(MXC_CPU_MX6DL))
721 type = "Dual-Lite";
722 else if (is_cpu_type(MXC_CPU_MX6SOLO))
723 type = "Solo";
724
725 printf("Board: conga-QMX6 %s\n", type);
726
727 return 0;
728}
729
730#ifdef CONFIG_MXC_SPI
731int board_spi_cs_gpio(unsigned bus, unsigned cs)
732{
733 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
734}
735#endif
736
737#ifdef CONFIG_CMD_BMODE
738static const struct boot_mode board_boot_modes[] = {
739
740 {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
741 {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
742 {NULL, 0},
743};
744#endif
745
746int misc_init_r(void)
747{
748#ifdef CONFIG_CMD_BMODE
749 add_board_boot_modes(board_boot_modes);
750#endif
751 return 0;
752}
753
754int board_late_init(void)
755{
756#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
757 if (is_mx6dq())
758 env_set("board_rev", "MX6Q");
759 else
760 env_set("board_rev", "MX6DL");
761#endif
762
763 return 0;
764}
765
766#ifdef CONFIG_SPL_BUILD
767#include <asm/arch/mx6-ddr.h>
768#include <spl.h>
769#include <linux/libfdt.h>
770#include <spi_flash.h>
771#include <spi.h>
772
773const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
774 .dram_sdclk_0 = 0x00000030,
775 .dram_sdclk_1 = 0x00000030,
776 .dram_cas = 0x00000030,
777 .dram_ras = 0x00000030,
778 .dram_reset = 0x00000030,
779 .dram_sdcke0 = 0x00003000,
780 .dram_sdcke1 = 0x00003000,
781 .dram_sdba2 = 0x00000000,
782 .dram_sdodt0 = 0x00000030,
783 .dram_sdodt1 = 0x00000030,
784 .dram_sdqs0 = 0x00000030,
785 .dram_sdqs1 = 0x00000030,
786 .dram_sdqs2 = 0x00000030,
787 .dram_sdqs3 = 0x00000030,
788 .dram_sdqs4 = 0x00000030,
789 .dram_sdqs5 = 0x00000030,
790 .dram_sdqs6 = 0x00000030,
791 .dram_sdqs7 = 0x00000030,
792 .dram_dqm0 = 0x00000030,
793 .dram_dqm1 = 0x00000030,
794 .dram_dqm2 = 0x00000030,
795 .dram_dqm3 = 0x00000030,
796 .dram_dqm4 = 0x00000030,
797 .dram_dqm5 = 0x00000030,
798 .dram_dqm6 = 0x00000030,
799 .dram_dqm7 = 0x00000030,
800};
801
802static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
803 .dram_sdclk_0 = 0x00000030,
804 .dram_sdclk_1 = 0x00000030,
805 .dram_cas = 0x00000030,
806 .dram_ras = 0x00000030,
807 .dram_reset = 0x00000030,
808 .dram_sdcke0 = 0x00003000,
809 .dram_sdcke1 = 0x00003000,
810 .dram_sdba2 = 0x00000000,
811 .dram_sdodt0 = 0x00000030,
812 .dram_sdodt1 = 0x00000030,
813 .dram_sdqs0 = 0x00000030,
814 .dram_sdqs1 = 0x00000030,
815 .dram_sdqs2 = 0x00000030,
816 .dram_sdqs3 = 0x00000030,
817 .dram_sdqs4 = 0x00000030,
818 .dram_sdqs5 = 0x00000030,
819 .dram_sdqs6 = 0x00000030,
820 .dram_sdqs7 = 0x00000030,
821 .dram_dqm0 = 0x00000030,
822 .dram_dqm1 = 0x00000030,
823 .dram_dqm2 = 0x00000030,
824 .dram_dqm3 = 0x00000030,
825 .dram_dqm4 = 0x00000030,
826 .dram_dqm5 = 0x00000030,
827 .dram_dqm6 = 0x00000030,
828 .dram_dqm7 = 0x00000030,
829};
830
831const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
832 .grp_ddr_type = 0x000C0000,
833 .grp_ddrmode_ctl = 0x00020000,
834 .grp_ddrpke = 0x00000000,
835 .grp_addds = 0x00000030,
836 .grp_ctlds = 0x00000030,
837 .grp_ddrmode = 0x00020000,
838 .grp_b0ds = 0x00000030,
839 .grp_b1ds = 0x00000030,
840 .grp_b2ds = 0x00000030,
841 .grp_b3ds = 0x00000030,
842 .grp_b4ds = 0x00000030,
843 .grp_b5ds = 0x00000030,
844 .grp_b6ds = 0x00000030,
845 .grp_b7ds = 0x00000030,
846};
847
848static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
849 .grp_ddr_type = 0x000c0000,
850 .grp_ddrmode_ctl = 0x00020000,
851 .grp_ddrpke = 0x00000000,
852 .grp_addds = 0x00000030,
853 .grp_ctlds = 0x00000030,
854 .grp_ddrmode = 0x00020000,
855 .grp_b0ds = 0x00000030,
856 .grp_b1ds = 0x00000030,
857 .grp_b2ds = 0x00000030,
858 .grp_b3ds = 0x00000030,
859 .grp_b4ds = 0x00000030,
860 .grp_b5ds = 0x00000030,
861 .grp_b6ds = 0x00000030,
862 .grp_b7ds = 0x00000030,
863};
864
865const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
866 .p0_mpwldectrl0 = 0x0016001A,
867 .p0_mpwldectrl1 = 0x0023001C,
868 .p1_mpwldectrl0 = 0x0028003A,
869 .p1_mpwldectrl1 = 0x001F002C,
870 .p0_mpdgctrl0 = 0x43440354,
871 .p0_mpdgctrl1 = 0x033C033C,
872 .p1_mpdgctrl0 = 0x43300368,
873 .p1_mpdgctrl1 = 0x03500330,
874 .p0_mprddlctl = 0x3228242E,
875 .p1_mprddlctl = 0x2C2C2636,
876 .p0_mpwrdlctl = 0x36323A38,
877 .p1_mpwrdlctl = 0x42324440,
878};
879
880const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
881 .p0_mpwldectrl0 = 0x00080016,
882 .p0_mpwldectrl1 = 0x001D0016,
883 .p1_mpwldectrl0 = 0x0018002C,
884 .p1_mpwldectrl1 = 0x000D001D,
885 .p0_mpdgctrl0 = 0x43200334,
886 .p0_mpdgctrl1 = 0x0320031C,
887 .p1_mpdgctrl0 = 0x0344034C,
888 .p1_mpdgctrl1 = 0x03380314,
889 .p0_mprddlctl = 0x3E36383A,
890 .p1_mprddlctl = 0x38363240,
891 .p0_mpwrdlctl = 0x36364238,
892 .p1_mpwrdlctl = 0x4230423E,
893};
894
895static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
896 .p0_mpwldectrl0 = 0x00480049,
897 .p0_mpwldectrl1 = 0x00410044,
898 .p0_mpdgctrl0 = 0x42480248,
899 .p0_mpdgctrl1 = 0x023C023C,
900 .p0_mprddlctl = 0x40424644,
901 .p0_mpwrdlctl = 0x34323034,
902};
903
904const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
905 .p0_mpwldectrl0 = 0x0043004B,
906 .p0_mpwldectrl1 = 0x003A003E,
907 .p1_mpwldectrl0 = 0x0047004F,
908 .p1_mpwldectrl1 = 0x004E0061,
909 .p0_mpdgctrl0 = 0x42500250,
910 .p0_mpdgctrl1 = 0x0238023C,
911 .p1_mpdgctrl0 = 0x42640264,
912 .p1_mpdgctrl1 = 0x02500258,
913 .p0_mprddlctl = 0x40424846,
914 .p1_mprddlctl = 0x46484842,
915 .p0_mpwrdlctl = 0x38382C30,
916 .p1_mpwrdlctl = 0x34343430,
917};
918
919static struct mx6_ddr3_cfg mem_ddr_2g = {
920 .mem_speed = 1600,
921 .density = 2,
922 .width = 16,
923 .banks = 8,
924 .rowaddr = 14,
925 .coladdr = 10,
926 .pagesz = 2,
927 .trcd = 1310,
928 .trcmin = 4875,
929 .trasmin = 3500,
930};
931
932static struct mx6_ddr3_cfg mem_ddr_4g = {
933 .mem_speed = 1600,
934 .density = 4,
935 .width = 16,
936 .banks = 8,
937 .rowaddr = 15,
938 .coladdr = 10,
939 .pagesz = 2,
940 .trcd = 1310,
941 .trcmin = 4875,
942 .trasmin = 3500,
943};
944
945static void ccgr_init(void)
946{
947 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
948
949 writel(0x00C03F3F, &ccm->CCGR0);
950 writel(0x0030FC03, &ccm->CCGR1);
951 writel(0x0FFFC000, &ccm->CCGR2);
952 writel(0x3FF00000, &ccm->CCGR3);
953 writel(0x00FFF300, &ccm->CCGR4);
954 writel(0x0F0000C3, &ccm->CCGR5);
955 writel(0x000003FF, &ccm->CCGR6);
956}
957
958
959struct mfgdata {
960 unsigned char tsize;
961
962 unsigned char ckcnt;
963
964 unsigned char cksum;
965
966 unsigned char serial[6];
967
968 unsigned char pn[16];
969};
970
971static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
972{
973 int remain = len;
974 unsigned char *sptr = src;
975 unsigned char *dptr = dst;
976
977 while (remain) {
978 if (*sptr) {
979 *dptr = *sptr;
980 dptr++;
981 }
982 sptr++;
983 remain--;
984 }
985 *dptr = 0x0;
986}
987
988#define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
989static bool is_2gb(void)
990{
991 struct spi_flash *spi;
992 int ret;
993 char buf[sizeof(struct mfgdata)];
994 struct mfgdata *data = (struct mfgdata *)buf;
995 unsigned char outbuf[32];
996
997 spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
998 CONFIG_ENV_SPI_CS,
999 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
1000 ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
1001 buf);
1002 if (ret)
1003 return false;
1004
1005
1006 conv_ascii(outbuf, data->pn, sizeof(data->pn));
1007 if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6))
1008 return true;
1009 else
1010 return false;
1011}
1012
1013static void spl_dram_init(int width)
1014{
1015 struct mx6_ddr_sysinfo sysinfo = {
1016
1017 .dsize = width / 32,
1018
1019 .cs_density = 32,
1020
1021 .ncs = 1,
1022 .cs1_mirror = 0,
1023 .rtt_wr = 2,
1024 .rtt_nom = 2,
1025 .walat = 0,
1026 .ralat = 5,
1027 .mif3_mode = 3,
1028 .bi_on = 1,
1029 .sde_to_rst = 0x0d,
1030 .rst_to_cke = 0x20,
1031 .refsel = 1,
1032 .refr = 7,
1033 };
1034
1035 if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
1036 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1037 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
1038 return;
1039 }
1040
1041 if (is_mx6dq()) {
1042 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1043 mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
1044 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
1045 sysinfo.walat = 1;
1046 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1047 mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
1048 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
1049 sysinfo.walat = 1;
1050 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1051 mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
1052 }
1053}
1054
1055void board_init_f(ulong dummy)
1056{
1057
1058 arch_cpu_init();
1059
1060 ccgr_init();
1061 gpr_init();
1062
1063
1064 board_early_init_f();
1065
1066
1067 timer_init();
1068
1069
1070 preloader_console_init();
1071
1072
1073 spl_init();
1074
1075
1076 if (is_cpu_type(MXC_CPU_MX6SOLO))
1077 spl_dram_init(32);
1078 else
1079 spl_dram_init(64);
1080
1081
1082 memset(__bss_start, 0, __bss_end - __bss_start);
1083
1084
1085 board_init_r(NULL, 0);
1086}
1087#endif
1088
