1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2016, NVIDIA CORPORATION. 4 */ 5 6#ifndef _TEGRA186_GPIO_PRIV_H_ 7#define _TEGRA186_GPIO_PRIV_H_ 8 9/* 10 * For each GPIO, there are a set of registers than affect it, all packed 11 * back-to-back. 12 */ 13#define TEGRA186_GPIO_ENABLE_CONFIG 0x00 14#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 15#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 16#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2 17#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3 18#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0 19#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1 20#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2 21#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3 22#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4) 23#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5) 24#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6) 25#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7) 26 27#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04 28 29#define TEGRA186_GPIO_INPUT 0x08 30 31#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 32#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 33 34#define TEGRA186_GPIO_OUTPUT_VALUE 0x10 35#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1 36 37#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 38 39/* 40 * 8 GPIOs are packed into a port. Their registers appear back-to-back in the 41 * port's address space. 42 */ 43#define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20 44#define TEGRA186_GPIO_PER_GPIO_COUNT 8 45 46/* 47 * Per-port registers are packed immediately following all of a port's 48 * per-GPIO registers. 49 */ 50#define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100 51#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4 52#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8 53 54/* 55 * The registers for multiple ports are packed together back-to-back to form 56 * the overall controller. 57 */ 58#define TEGRA186_GPIO_PER_PORT_STRIDE 0x200 59 60#endif 61