1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Motorola MC5275EVB board. 4 * 5 * By Arthur Shipkowski <art@videon-central.com> 6 * Copyright (C) 2005 Videon Central, Inc. 7 * 8 * Based off of M5272C3 board code by Josef Baumgartner 9 * <josef.baumgartner@telex.de> 10 */ 11 12/* 13 * board/config.h - configuration options, board specific 14 */ 15 16#ifndef _M5275EVB_H 17#define _M5275EVB_H 18 19/* 20 * High Level Configuration Options 21 * (easy to change) 22 */ 23 24#define CONFIG_MCFTMR 25 26#define CONFIG_MCFUART 27#define CONFIG_SYS_UART_PORT (0) 28 29/* Configuration for environment 30 * Environment is embedded in u-boot in the second sector of the flash 31 */ 32#ifndef CONFIG_MONITOR_IS_IN_RAM 33#define CONFIG_ENV_OFFSET 0x4000 34#define CONFIG_ENV_SECT_SIZE 0x2000 35#else 36#define CONFIG_ENV_ADDR 0xffe04000 37#define CONFIG_ENV_SECT_SIZE 0x2000 38#endif 39 40#define LDS_BOARD_TEXT \ 41 . = DEFINED(env_offset) ? env_offset : .; \ 42 env/embedded.o(.text); 43 44/* 45 * BOOTP options 46 */ 47#define CONFIG_BOOTP_BOOTFILESIZE 48 49/* Available command configuration */ 50 51#define CONFIG_MCFFEC 52#ifdef CONFIG_MCFFEC 53#define CONFIG_MII_INIT 1 54#define CONFIG_SYS_DISCOVER_PHY 55#define CONFIG_SYS_RX_ETH_BUFFER 8 56#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57#define CONFIG_SYS_FEC0_PINMUX 0 58#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 59#define CONFIG_SYS_FEC1_PINMUX 0 60#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 61#define MCFFEC_TOUT_LOOP 50000 62#define CONFIG_HAS_ETH1 63/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 64#ifndef CONFIG_SYS_DISCOVER_PHY 65#define FECDUPLEX FULL 66#define FECSPEED _100BASET 67#else 68#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 69#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 70#endif 71#endif 72#endif 73 74/* I2C */ 75#define CONFIG_SYS_I2C 76#define CONFIG_SYS_I2C_FSL 77#define CONFIG_SYS_FSL_I2C_SPEED 80000 78#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 79#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 80#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 81#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) 82#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) 83#define CONFIG_SYS_I2C_PINMUX_SET (0x000F) 84 85#define CONFIG_SYS_LOAD_ADDR 0x800000 86 87#define CONFIG_BOOTCOMMAND "bootm ffe40000" 88#define CONFIG_SYS_MEMTEST_START 0x400 89#define CONFIG_SYS_MEMTEST_END 0x380000 90 91#ifdef CONFIG_MCFFEC 92# define CONFIG_NET_RETRY_COUNT 5 93# define CONFIG_OVERWRITE_ETHADDR_ONCE 94#endif /* FEC_ENET */ 95 96#define CONFIG_EXTRA_ENV_SETTINGS \ 97 "netdev=eth0\0" \ 98 "loadaddr=10000\0" \ 99 "uboot=u-boot.bin\0" \ 100 "load=tftp ${loadaddr} ${uboot}\0" \ 101 "upd=run load; run prog\0" \ 102 "prog=prot off ffe00000 ffe3ffff;" \ 103 "era ffe00000 ffe3ffff;" \ 104 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 105 "save\0" \ 106 "" 107 108#define CONFIG_SYS_CLK 150000000 109 110/* 111 * Low Level Configuration Settings 112 * (address mappings, register initial values, etc.) 113 * You should know what you are doing if you make changes here. 114 */ 115 116#define CONFIG_SYS_MBAR 0x40000000 117 118/*----------------------------------------------------------------------- 119 * Definitions for initial stack pointer and data area (in DPRAM) 120 */ 121#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 122#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 123#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 124#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 125 126/*----------------------------------------------------------------------- 127 * Start addresses for the final memory configuration 128 * (Set up by the startup code) 129 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 130 */ 131#define CONFIG_SYS_SDRAM_BASE 0x00000000 132#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 133#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 134 135#ifdef CONFIG_MONITOR_IS_IN_RAM 136#define CONFIG_SYS_MONITOR_BASE 0x20000 137#else 138#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 139#endif 140 141#define CONFIG_SYS_MONITOR_LEN 0x20000 142#define CONFIG_SYS_MALLOC_LEN (256 << 10) 143#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 144 145/* 146 * For booting Linux, the board info and command line data 147 * have to be in the first 8 MB of memory, since this is 148 * the maximum mapped by the Linux kernel during initialization ?? 149 */ 150#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 151#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 152 153/*----------------------------------------------------------------------- 154 * FLASH organization 155 */ 156#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 157#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 158#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 159 160#define CONFIG_SYS_FLASH_SIZE 0x200000 161 162/*----------------------------------------------------------------------- 163 * Cache Configuration 164 */ 165#define CONFIG_SYS_CACHELINE_SIZE 16 166 167#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 168 CONFIG_SYS_INIT_RAM_SIZE - 8) 169#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 170 CONFIG_SYS_INIT_RAM_SIZE - 4) 171#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 172#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 173 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 174 CF_ACR_EN | CF_ACR_SM_ALL) 175#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 176 CF_CACR_DISD | CF_CACR_INVI | \ 177 CF_CACR_CEIB | CF_CACR_DCM | \ 178 CF_CACR_EUSP) 179 180/*----------------------------------------------------------------------- 181 * Memory bank definitions 182 */ 183#define CONFIG_SYS_CS0_BASE 0xffe00000 184#define CONFIG_SYS_CS0_CTRL 0x00001980 185#define CONFIG_SYS_CS0_MASK 0x001F0001 186 187#define CONFIG_SYS_CS1_BASE 0x30000000 188#define CONFIG_SYS_CS1_CTRL 0x00001900 189#define CONFIG_SYS_CS1_MASK 0x00070001 190 191/*----------------------------------------------------------------------- 192 * Port configuration 193 */ 194#define CONFIG_SYS_FECI2C 0x0FA0 195 196#endif /* _M5275EVB_H */ 197