1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF5475 board. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M5475EVB_H 14#define _M5475EVB_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21#define CONFIG_MCFUART 22#define CONFIG_SYS_UART_PORT (0) 23 24#undef CONFIG_HW_WATCHDOG 25#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 26 27#define CONFIG_SLTTMR 28 29#define CONFIG_FSLDMAFEC 30#ifdef CONFIG_FSLDMAFEC 31# define CONFIG_MII_INIT 1 32# define CONFIG_HAS_ETH1 33 34# define CONFIG_SYS_DMA_USE_INTSRAM 1 35# define CONFIG_SYS_DISCOVER_PHY 36# define CONFIG_SYS_RX_ETH_BUFFER 32 37# define CONFIG_SYS_TX_ETH_BUFFER 48 38# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 39 40# define CONFIG_SYS_FEC0_PINMUX 0 41# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 42# define CONFIG_SYS_FEC1_PINMUX 0 43# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 44 45# define MCFFEC_TOUT_LOOP 50000 46/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 47# ifndef CONFIG_SYS_DISCOVER_PHY 48# define FECDUPLEX FULL 49# define FECSPEED _100BASET 50# else 51# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 52# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53# endif 54# endif /* CONFIG_SYS_DISCOVER_PHY */ 55 56# define CONFIG_IPADDR 192.162.1.2 57# define CONFIG_NETMASK 255.255.255.0 58# define CONFIG_SERVERIP 192.162.1.1 59# define CONFIG_GATEWAYIP 192.162.1.1 60 61#endif 62 63#ifdef CONFIG_CMD_USB 64# define CONFIG_USB_OHCI_NEW 65 66# define CONFIG_PCI_OHCI 67 68# undef CONFIG_SYS_USB_OHCI_BOARD_INIT 69# undef CONFIG_SYS_USB_OHCI_CPU_INIT 70# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 71# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 72# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 73#endif 74 75/* I2C */ 76#define CONFIG_SYS_I2C 77#define CONFIG_SYS_I2C_FSL 78#define CONFIG_SYS_FSL_I2C_SPEED 80000 79#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 80#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 81#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 82 83/* PCI */ 84#ifdef CONFIG_CMD_PCI 85#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 86 87#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 88 89#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 90#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 91#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 92 93#define CONFIG_SYS_PCI_IO_BUS 0x71000000 94#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 95#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 96 97#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 98#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 99#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 100#endif 101 102#define CONFIG_UDP_CHECKSUM 103 104#ifdef CONFIG_MCFFEC 105# define CONFIG_IPADDR 192.162.1.2 106# define CONFIG_NETMASK 255.255.255.0 107# define CONFIG_SERVERIP 192.162.1.1 108# define CONFIG_GATEWAYIP 192.162.1.1 109#endif /* FEC_ENET */ 110 111#define CONFIG_HOSTNAME "M547xEVB" 112#define CONFIG_EXTRA_ENV_SETTINGS \ 113 "netdev=eth0\0" \ 114 "loadaddr=10000\0" \ 115 "u-boot=u-boot.bin\0" \ 116 "load=tftp ${loadaddr) ${u-boot}\0" \ 117 "upd=run load; run prog\0" \ 118 "prog=prot off bank 1;" \ 119 "era ff800000 ff83ffff;" \ 120 "cp.b ${loadaddr} ff800000 ${filesize};"\ 121 "save\0" \ 122 "" 123 124#define CONFIG_PRAM 512 /* 512 KB */ 125 126#define CONFIG_SYS_LOAD_ADDR 0x00010000 127 128#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 129#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 130 131#define CONFIG_SYS_MBAR 0xF0000000 132#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 133#define CONFIG_SYS_INTSRAMSZ 0x8000 134 135/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 136 137/* 138 * Low Level Configuration Settings 139 * (address mappings, register initial values, etc.) 140 * You should know what you are doing if you make changes here. 141 */ 142/*----------------------------------------------------------------------- 143 * Definitions for initial stack pointer and data area (in DPRAM) 144 */ 145#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 146#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 147#define CONFIG_SYS_INIT_RAM_CTRL 0x21 148#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 149#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 150#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 151#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 152#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 153 154/*----------------------------------------------------------------------- 155 * Start addresses for the final memory configuration 156 * (Set up by the startup code) 157 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 158 */ 159#define CONFIG_SYS_SDRAM_BASE 0x00000000 160#define CONFIG_SYS_SDRAM_CFG1 0x73711630 161#define CONFIG_SYS_SDRAM_CFG2 0x46770000 162#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 163#define CONFIG_SYS_SDRAM_EMOD 0x40010000 164#define CONFIG_SYS_SDRAM_MODE 0x018D0000 165#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 166#ifdef CONFIG_SYS_DRAMSZ1 167# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 168#else 169# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 170#endif 171 172#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 173#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 174 175#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 176#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 177 178#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 179 180/* Reserve 256 kB for malloc() */ 181#define CONFIG_SYS_MALLOC_LEN (256 << 10) 182/* 183 * For booting Linux, the board info and command line data 184 * have to be in the first 8 MB of memory, since this is 185 * the maximum mapped by the Linux kernel during initialization ?? 186 */ 187#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 188 189/*----------------------------------------------------------------------- 190 * FLASH organization 191 */ 192#ifdef CONFIG_SYS_FLASH_CFI 193# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 194# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 195# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 196#ifdef CONFIG_SYS_NOR1SZ 197# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 198# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 199# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 200#else 201# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 202# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 203#endif 204#endif 205 206/* Configuration for environment 207 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 208 * First time runing may have env crc error warning if there is 209 * no correct environment on the flash. 210 */ 211#define CONFIG_ENV_OFFSET 0x40000 212#define CONFIG_ENV_SECT_SIZE 0x10000 213 214/*----------------------------------------------------------------------- 215 * Cache Configuration 216 */ 217#define CONFIG_SYS_CACHELINE_SIZE 16 218 219#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 220 CONFIG_SYS_INIT_RAM_SIZE - 8) 221#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 222 CONFIG_SYS_INIT_RAM_SIZE - 4) 223#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 224 CF_CACR_IDCM) 225#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 226#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 227 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 228 CF_ACR_EN | CF_ACR_SM_ALL) 229#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 230 CF_CACR_IEC | CF_CACR_ICINVA) 231#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 232 CF_CACR_DEC | CF_CACR_DDCM_P | \ 233 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 234 235/*----------------------------------------------------------------------- 236 * Chipselect bank definitions 237 */ 238/* 239 * CS0 - NOR Flash 1, 2, 4, or 8MB 240 * CS1 - NOR Flash 241 * CS2 - Available 242 * CS3 - Available 243 * CS4 - Available 244 * CS5 - Available 245 */ 246#define CONFIG_SYS_CS0_BASE 0xFF800000 247#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 248#define CONFIG_SYS_CS0_CTRL 0x00101980 249 250#ifdef CONFIG_SYS_NOR1SZ 251#define CONFIG_SYS_CS1_BASE 0xE0000000 252#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 253#define CONFIG_SYS_CS1_CTRL 0x00101D80 254#endif 255 256#endif /* _M5475EVB_H */ 257