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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "../board/freescale/common/ics307_clk.h"
14
15#ifdef CONFIG_SDCARD
16#define CONFIG_RAMBOOT_SDCARD 1
17#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
18#endif
19
20#ifdef CONFIG_SPIFLASH
21#define CONFIG_RAMBOOT_SPIFLASH 1
22#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
23#endif
24
25#ifndef CONFIG_RESET_VECTOR_ADDRESS
26#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
27#endif
28
29#ifndef CONFIG_SYS_MONITOR_BASE
30#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
31#endif
32
33#define CONFIG_PCI1 1
34#define CONFIG_PCIE1 1
35#define CONFIG_PCIE2 1
36#define CONFIG_PCIE3 1
37#define CONFIG_FSL_PCI_INIT 1
38#define CONFIG_PCI_INDIRECT_BRIDGE 1
39#define CONFIG_FSL_PCIE_RESET 1
40#define CONFIG_SYS_PCI_64BIT 1
41
42
43#define CONFIG_ENV_OVERWRITE
44
45#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
46#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
47#define CONFIG_ICS307_REFCLK_HZ 33333000
48
49
50
51
52#define CONFIG_L2_CACHE
53#define CONFIG_BTB
54
55#define CONFIG_ENABLE_36BIT_PHYS 1
56
57#ifdef CONFIG_PHYS_64BIT
58#define CONFIG_ADDR_MAP 1
59#define CONFIG_SYS_NUM_ADDR_MAP 16
60#endif
61
62#define CONFIG_SYS_MEMTEST_START 0x00010000
63#define CONFIG_SYS_MEMTEST_END 0x1f000000
64
65
66
67
68#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
69#ifdef CONFIG_PHYS_64BIT
70#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
71#else
72#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
73#endif
74#define CONFIG_SYS_L2_SIZE (512 << 10)
75#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
76
77#define CONFIG_SYS_CCSRBAR 0xffe00000
78#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79
80#if defined(CONFIG_NAND_SPL)
81#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
82#endif
83
84
85#define CONFIG_VERY_BIG_RAM
86#define CONFIG_SPD_EEPROM
87#define CONFIG_DDR_SPD
88
89#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
90#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
91
92#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
93#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
94
95#define CONFIG_DIMM_SLOTS_PER_CTLR 1
96#define CONFIG_CHIP_SELECTS_PER_CTRL 2
97
98
99#define SPD_EEPROM_ADDRESS 0x51
100#define CONFIG_SYS_SPD_BUS_NUM 1
101
102
103#define CONFIG_SYS_SDRAM_SIZE 256
104#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
105#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
106#define CONFIG_SYS_DDR_TIMING_3 0x00000000
107#define CONFIG_SYS_DDR_TIMING_0 0x00260802
108#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
109#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
110#define CONFIG_SYS_DDR_MODE_1 0x00480432
111#define CONFIG_SYS_DDR_MODE_2 0x00000000
112#define CONFIG_SYS_DDR_INTERVAL 0x06180100
113#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
114#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
115#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
116#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
117#define CONFIG_SYS_DDR_CONTROL 0xC3008000
118#define CONFIG_SYS_DDR_CONTROL2 0x04400010
119
120#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
121#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
122#define CONFIG_SYS_DDR_SBE 0x00010000
123
124
125#ifndef CONFIG_SPD_EEPROM
126#error ("CONFIG_SPD_EEPROM is required")
127#endif
128
129#undef CONFIG_CLOCKS_IN_MHZ
130
131
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134
135
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151
152
153
154#define CONFIG_SYS_FLASH_BASE 0xe0000000
155#ifdef CONFIG_PHYS_64BIT
156#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
157#else
158#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
159#endif
160
161#define CONFIG_FLASH_BR_PRELIM \
162 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
163#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
164
165#define CONFIG_SYS_BR1_PRELIM \
166 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
167 | BR_PS_16 | BR_V)
168#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
169
170#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
171 CONFIG_SYS_FLASH_BASE_PHYS }
172#define CONFIG_SYS_FLASH_QUIET_TEST
173#define CONFIG_FLASH_SHOW_PROGRESS 45
174
175#define CONFIG_SYS_MAX_FLASH_BANKS 2
176#define CONFIG_SYS_MAX_FLASH_SECT 1024
177#undef CONFIG_SYS_FLASH_CHECKSUM
178#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
179#define CONFIG_SYS_FLASH_WRITE_TOUT 500
180
181#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
182#define CONFIG_SYS_RAMBOOT
183#else
184#undef CONFIG_SYS_RAMBOOT
185#endif
186
187#define CONFIG_SYS_FLASH_EMPTY_INFO
188#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
189
190#define CONFIG_HWCONFIG
191#define CONFIG_FSL_PIXIS 1
192#define PIXIS_BASE 0xffdf0000
193#ifdef CONFIG_PHYS_64BIT
194#define PIXIS_BASE_PHYS 0xfffdf0000ull
195#else
196#define PIXIS_BASE_PHYS PIXIS_BASE
197#endif
198
199#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
200#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
201
202#define PIXIS_ID 0x0
203#define PIXIS_VER 0x1
204#define PIXIS_PVER 0x2
205#define PIXIS_CSR 0x3
206#define PIXIS_RST 0x4
207#define PIXIS_PWR 0x5
208#define PIXIS_AUX 0x6
209#define PIXIS_SPD 0x7
210#define PIXIS_AUX2 0x8
211#define PIXIS_VCTL 0x10
212#define PIXIS_VSTAT 0x11
213#define PIXIS_VCFGEN0 0x12
214#define PIXIS_VCFGEN1 0x13
215#define PIXIS_VCORE0 0x14
216#define PIXIS_VBOOT 0x16
217#define PIXIS_VBOOT_LBMAP 0xe0
218#define PIXIS_VBOOT_LBMAP_NOR0 0x00
219#define PIXIS_VBOOT_LBMAP_NOR1 0x01
220#define PIXIS_VBOOT_LBMAP_NOR2 0x02
221#define PIXIS_VBOOT_LBMAP_NOR3 0x03
222#define PIXIS_VBOOT_LBMAP_PJET 0x04
223#define PIXIS_VBOOT_LBMAP_NAND 0x05
224#define PIXIS_VSPEED0 0x17
225#define PIXIS_VSPEED1 0x18
226#define PIXIS_VSPEED2 0x19
227#define PIXIS_VSYSCLK0 0x1A
228#define PIXIS_VSYSCLK1 0x1B
229#define PIXIS_VSYSCLK2 0x1C
230#define PIXIS_VDDRCLK0 0x1D
231#define PIXIS_VDDRCLK1 0x1E
232#define PIXIS_VDDRCLK2 0x1F
233#define PIXIS_VWATCH 0x24
234#define PIXIS_LED 0x25
235
236#define PIXIS_SPD_SYSCLK 0x7
237
238
239#define PIXIS_VCLKH 0x19
240#define PIXIS_VCLKL 0x1A
241#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
242
243#define CONFIG_SYS_INIT_RAM_LOCK 1
244#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
245#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
246
247#define CONFIG_SYS_GBL_DATA_OFFSET \
248 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
249#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
250
251#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
252#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
253
254#ifndef CONFIG_NAND_SPL
255#define CONFIG_SYS_NAND_BASE 0xffa00000
256#ifdef CONFIG_PHYS_64BIT
257#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
258#else
259#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
260#endif
261#else
262#define CONFIG_SYS_NAND_BASE 0xfff00000
263#ifdef CONFIG_PHYS_64BIT
264#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
265#else
266#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
267#endif
268#endif
269#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
270 CONFIG_SYS_NAND_BASE + 0x40000, \
271 CONFIG_SYS_NAND_BASE + 0x80000, \
272 CONFIG_SYS_NAND_BASE + 0xC0000}
273#define CONFIG_SYS_MAX_NAND_DEVICE 4
274#define CONFIG_NAND_FSL_ELBC 1
275#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
276
277
278#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
279#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
280#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
281#define CONFIG_SYS_NAND_U_BOOT_START \
282 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
283#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
284#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
285#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
286
287
288#define CONFIG_SYS_NAND_BR_PRELIM \
289 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
290 | (2<<BR_DECC_SHIFT) \
291 | BR_PS_8 \
292 | BR_MS_FCM \
293 | BR_V)
294#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
295 | OR_FCM_PGS \
296 | OR_FCM_CSCT \
297 | OR_FCM_CST \
298 | OR_FCM_CHT \
299 | OR_FCM_SCY_1 \
300 | OR_FCM_TRLX \
301 | OR_FCM_EHTR)
302
303#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
304#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
305#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
306#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
307
308#define CONFIG_SYS_BR4_PRELIM \
309 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
310 | (2<<BR_DECC_SHIFT) \
311 | BR_PS_8 \
312 | BR_MS_FCM \
313 | BR_V)
314#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM
315#define CONFIG_SYS_BR5_PRELIM \
316 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
317 | (2<<BR_DECC_SHIFT) \
318 | BR_PS_8 \
319 | BR_MS_FCM \
320 | BR_V)
321#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM
322
323#define CONFIG_SYS_BR6_PRELIM \
324 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
325 | (2<<BR_DECC_SHIFT) \
326 | BR_PS_8 \
327 | BR_MS_FCM \
328 | BR_V)
329#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM
330
331
332
333
334
335#define CONFIG_SYS_NS16550_SERIAL
336#define CONFIG_SYS_NS16550_REG_SIZE 1
337#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
338#ifdef CONFIG_NAND_SPL
339#define CONFIG_NS16550_MIN_FUNCTIONS
340#endif
341
342#define CONFIG_SYS_BAUDRATE_TABLE \
343 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
344
345#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
346#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
347
348
349
350
351#define CONFIG_SYS_I2C
352#define CONFIG_SYS_I2C_FSL
353#define CONFIG_SYS_FSL_I2C_SPEED 400000
354#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
355#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
356#define CONFIG_SYS_FSL_I2C2_SPEED 400000
357#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
358#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
359#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
360
361
362
363
364#define CONFIG_ID_EEPROM
365#ifdef CONFIG_ID_EEPROM
366#define CONFIG_SYS_I2C_EEPROM_NXID
367#endif
368#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
369#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
370#define CONFIG_SYS_EEPROM_BUS_NUM 1
371
372
373
374
375
376
377#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
378#ifdef CONFIG_PHYS_64BIT
379#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
380#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
381#else
382#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
383#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
384#endif
385#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
386#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
387#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
388#ifdef CONFIG_PHYS_64BIT
389#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
390#else
391#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
392#endif
393#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
394
395
396#define CONFIG_SYS_PCIE1_NAME "Slot 1"
397#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
398#ifdef CONFIG_PHYS_64BIT
399#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
400#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
401#else
402#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
403#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
404#endif
405#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000
406#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
407#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
408#ifdef CONFIG_PHYS_64BIT
409#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
410#else
411#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
412#endif
413#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
414
415
416#define CONFIG_SYS_PCIE2_NAME "Slot 2"
417#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
418#ifdef CONFIG_PHYS_64BIT
419#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
420#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
421#else
422#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
423#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
424#endif
425#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000
426#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
427#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
428#ifdef CONFIG_PHYS_64BIT
429#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
430#else
431#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
432#endif
433#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
434
435
436#define CONFIG_SYS_PCIE3_NAME "Slot 3"
437#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
438#ifdef CONFIG_PHYS_64BIT
439#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
440#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
441#else
442#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
443#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
444#endif
445#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
446#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
447#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
448#ifdef CONFIG_PHYS_64BIT
449#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
450#else
451#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
452#endif
453#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
454
455#if defined(CONFIG_PCI)
456
457#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
458
459
460
461
462
463
464#if defined(CONFIG_VIDEO)
465#define CONFIG_BIOSEMU
466#define CONFIG_ATI_RADEON_FB
467#define CONFIG_VIDEO_LOGO
468#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
469#endif
470
471#undef CONFIG_EEPRO100
472#undef CONFIG_TULIP
473
474#ifndef CONFIG_PCI_PNP
475 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
476 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
477 #define PCI_IDSEL_NUMBER 0x11
478#endif
479
480#define CONFIG_PCI_SCAN_SHOW
481
482#endif
483
484
485#define CONFIG_SYS_SATA_MAX_DEVICE 2
486#define CONFIG_SATA1
487#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
488#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
489#define CONFIG_SATA2
490#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
491#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
492
493#ifdef CONFIG_FSL_SATA
494#define CONFIG_LBA48
495#endif
496
497#if defined(CONFIG_TSEC_ENET)
498
499#define CONFIG_MII_DEFAULT_TSEC 1
500#define CONFIG_TSEC1 1
501#define CONFIG_TSEC1_NAME "eTSEC1"
502#define CONFIG_TSEC3 1
503#define CONFIG_TSEC3_NAME "eTSEC3"
504
505#define CONFIG_FSL_SGMII_RISER 1
506#define SGMII_RISER_PHY_OFFSET 0x1c
507
508#define TSEC1_PHY_ADDR 1
509#define TSEC3_PHY_ADDR 0
510
511#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
512#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
513
514#define TSEC1_PHYIDX 0
515#define TSEC3_PHYIDX 0
516
517#define CONFIG_ETHPRIME "eTSEC1"
518
519#endif
520
521
522
523
524
525#if defined(CONFIG_SYS_RAMBOOT)
526#if defined(CONFIG_RAMBOOT_SPIFLASH)
527#define CONFIG_ENV_SIZE 0x2000
528#define CONFIG_ENV_OFFSET 0xF0000
529#define CONFIG_ENV_SECT_SIZE 0x10000
530#elif defined(CONFIG_RAMBOOT_SDCARD)
531#define CONFIG_FSL_FIXED_MMC_LOCATION
532#define CONFIG_ENV_SIZE 0x2000
533#define CONFIG_SYS_MMC_ENV_DEV 0
534#else
535 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
536 #define CONFIG_ENV_SIZE 0x2000
537#endif
538#else
539 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
540 #define CONFIG_ENV_SIZE 0x2000
541 #define CONFIG_ENV_SECT_SIZE 0x20000
542#endif
543
544#define CONFIG_LOADS_ECHO 1
545#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
546
547#undef CONFIG_WATCHDOG
548
549#ifdef CONFIG_MMC
550#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
551#endif
552
553
554
555
556#define CONFIG_HAS_FSL_MPH_USB
557#ifdef CONFIG_HAS_FSL_MPH_USB
558#ifdef CONFIG_USB_EHCI_HCD
559#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
560#define CONFIG_USB_EHCI_FSL
561#endif
562#endif
563
564
565
566
567#define CONFIG_SYS_LOAD_ADDR 0x2000000
568
569
570
571
572
573
574#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
575#define CONFIG_SYS_BOOTM_LEN (64 << 20)
576
577#if defined(CONFIG_CMD_KGDB)
578#define CONFIG_KGDB_BAUDRATE 230400
579#endif
580
581
582
583
584
585
586#if defined(CONFIG_TSEC_ENET)
587#define CONFIG_HAS_ETH0
588#define CONFIG_HAS_ETH1
589#define CONFIG_HAS_ETH2
590#define CONFIG_HAS_ETH3
591#endif
592
593#define CONFIG_IPADDR 192.168.1.254
594
595#define CONFIG_HOSTNAME "unknown"
596#define CONFIG_ROOTPATH "/opt/nfsroot"
597#define CONFIG_BOOTFILE "uImage"
598#define CONFIG_UBOOTPATH u-boot.bin
599
600#define CONFIG_SERVERIP 192.168.1.1
601#define CONFIG_GATEWAYIP 192.168.1.1
602#define CONFIG_NETMASK 255.255.255.0
603
604
605#define CONFIG_LOADADDR 1000000
606
607#define CONFIG_EXTRA_ENV_SETTINGS \
608"netdev=eth0\0" \
609"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
610"tftpflash=tftpboot $loadaddr $uboot; " \
611 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
612 " +$filesize; " \
613 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
614 " +$filesize; " \
615 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
616 " $filesize; " \
617 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
618 " +$filesize; " \
619 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
620 " $filesize\0" \
621"consoledev=ttyS0\0" \
622"ramdiskaddr=2000000\0" \
623"ramdiskfile=8536ds/ramdisk.uboot\0" \
624"fdtaddr=1e00000\0" \
625"fdtfile=8536ds/mpc8536ds.dtb\0" \
626"bdev=sda3\0" \
627"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
628
629#define CONFIG_HDBOOT \
630 "setenv bootargs root=/dev/$bdev rw " \
631 "console=$consoledev,$baudrate $othbootargs;" \
632 "tftp $loadaddr $bootfile;" \
633 "tftp $fdtaddr $fdtfile;" \
634 "bootm $loadaddr - $fdtaddr"
635
636#define CONFIG_NFSBOOTCOMMAND \
637 "setenv bootargs root=/dev/nfs rw " \
638 "nfsroot=$serverip:$rootpath " \
639 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
640 "console=$consoledev,$baudrate $othbootargs;" \
641 "tftp $loadaddr $bootfile;" \
642 "tftp $fdtaddr $fdtfile;" \
643 "bootm $loadaddr - $fdtaddr"
644
645#define CONFIG_RAMBOOTCOMMAND \
646 "setenv bootargs root=/dev/ram rw " \
647 "console=$consoledev,$baudrate $othbootargs;" \
648 "tftp $ramdiskaddr $ramdiskfile;" \
649 "tftp $loadaddr $bootfile;" \
650 "tftp $fdtaddr $fdtfile;" \
651 "bootm $loadaddr $ramdiskaddr $fdtaddr"
652
653#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
654
655#endif
656