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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "../board/freescale/common/ics307_clk.h"
14
15#ifndef CONFIG_RESET_VECTOR_ADDRESS
16#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
17#endif
18
19#ifndef CONFIG_SYS_MONITOR_BASE
20#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
21#endif
22
23
24
25#define CONFIG_PCIE1 1
26#define CONFIG_PCIE2 1
27#define CONFIG_PCIE3 1
28#define CONFIG_FSL_PCI_INIT 1
29#define CONFIG_PCI_INDIRECT_BRIDGE 1
30#define CONFIG_FSL_PCIE_RESET 1
31#define CONFIG_SYS_PCI_64BIT 1
32
33#define CONFIG_ENV_OVERWRITE
34
35#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
36#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
37#define CONFIG_ICS307_REFCLK_HZ 33333000
38
39
40
41
42#define CONFIG_L2_CACHE
43#define CONFIG_BTB
44
45#define CONFIG_ENABLE_36BIT_PHYS 1
46
47#ifdef CONFIG_PHYS_64BIT
48#define CONFIG_ADDR_MAP 1
49#define CONFIG_SYS_NUM_ADDR_MAP 16
50#endif
51
52#define CONFIG_SYS_MEMTEST_START 0x00000000
53#define CONFIG_SYS_MEMTEST_END 0x7fffffff
54
55
56
57
58#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
59#ifdef CONFIG_PHYS_64BIT
60#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
61#else
62#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
63#endif
64#define CONFIG_SYS_L2_SIZE (512 << 10)
65#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
66
67#define CONFIG_SYS_CCSRBAR 0xffe00000
68#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
69
70#if defined(CONFIG_NAND_SPL)
71#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
72#endif
73
74
75#define CONFIG_VERY_BIG_RAM
76#define CONFIG_SPD_EEPROM
77#define CONFIG_DDR_SPD
78
79#define CONFIG_DDR_ECC
80#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
81#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
82
83#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
84#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
85
86#define CONFIG_DIMM_SLOTS_PER_CTLR 1
87#define CONFIG_CHIP_SELECTS_PER_CTRL 2
88
89
90#define CONFIG_SYS_SPD_BUS_NUM 1
91#define SPD_EEPROM_ADDRESS1 0x51
92#define SPD_EEPROM_ADDRESS2 0x52
93
94
95#define CONFIG_SYS_SDRAM_SIZE 512
96#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
97#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202
98#define CONFIG_SYS_DDR_TIMING_3 0x00020000
99#define CONFIG_SYS_DDR_TIMING_0 0x00260802
100#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
101#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
102#define CONFIG_SYS_DDR_MODE_1 0x00440462
103#define CONFIG_SYS_DDR_MODE_2 0x00000000
104#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
105#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
106#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
107#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
108#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
109#define CONFIG_SYS_DDR_CONTROL 0xc3000008
110#define CONFIG_SYS_DDR_CONTROL2 0x24400000
111
112#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
113#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
114#define CONFIG_SYS_DDR_SBE 0x00010000
115
116
117
118
119#ifndef CONFIG_SPD_EEPROM
120#error ("CONFIG_SPD_EEPROM is required")
121#endif
122
123#undef CONFIG_CLOCKS_IN_MHZ
124
125
126
127
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145
146
147
148#define CONFIG_SYS_FLASH_BASE 0xe0000000
149#ifdef CONFIG_PHYS_64BIT
150#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
151#else
152#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
153#endif
154
155#define CONFIG_FLASH_BR_PRELIM \
156 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
157#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
158
159#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
160#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
161
162#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
163#define CONFIG_SYS_FLASH_QUIET_TEST
164#define CONFIG_FLASH_SHOW_PROGRESS 45
165
166#define CONFIG_SYS_MAX_FLASH_BANKS 2
167#define CONFIG_SYS_MAX_FLASH_SECT 1024
168#undef CONFIG_SYS_FLASH_CHECKSUM
169#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
170#define CONFIG_SYS_FLASH_WRITE_TOUT 500
171
172#undef CONFIG_SYS_RAMBOOT
173
174#define CONFIG_SYS_FLASH_EMPTY_INFO
175#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
176
177#define CONFIG_HWCONFIG
178#define CONFIG_FSL_PIXIS 1
179#define PIXIS_BASE 0xffdf0000
180#ifdef CONFIG_PHYS_64BIT
181#define PIXIS_BASE_PHYS 0xfffdf0000ull
182#else
183#define PIXIS_BASE_PHYS PIXIS_BASE
184#endif
185
186#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
187#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
188
189#define PIXIS_ID 0x0
190#define PIXIS_VER 0x1
191#define PIXIS_PVER 0x2
192#define PIXIS_CSR 0x3
193#define PIXIS_RST 0x4
194#define PIXIS_PWR 0x5
195#define PIXIS_AUX 0x6
196#define PIXIS_SPD 0x7
197#define PIXIS_AUX2 0x8
198#define PIXIS_VCTL 0x10
199#define PIXIS_VSTAT 0x11
200#define PIXIS_VCFGEN0 0x12
201#define PIXIS_VCFGEN1 0x13
202#define PIXIS_VCORE0 0x14
203#define PIXIS_VBOOT 0x16
204#define PIXIS_VBOOT_LBMAP 0xc0
205#define PIXIS_VBOOT_LBMAP_NOR0 0x00
206#define PIXIS_VBOOT_LBMAP_PJET 0x01
207#define PIXIS_VBOOT_LBMAP_NAND 0x02
208#define PIXIS_VBOOT_LBMAP_NOR1 0x03
209#define PIXIS_VSPEED0 0x17
210#define PIXIS_VSPEED1 0x18
211#define PIXIS_VSPEED2 0x19
212#define PIXIS_VSYSCLK0 0x1C
213#define PIXIS_VSYSCLK1 0x1D
214#define PIXIS_VSYSCLK2 0x1E
215#define PIXIS_VDDRCLK0 0x1F
216#define PIXIS_VDDRCLK1 0x20
217#define PIXIS_VDDRCLK2 0x21
218#define PIXIS_VWATCH 0x24
219#define PIXIS_LED 0x25
220
221#define PIXIS_SPD_SYSCLK_MASK 0x7
222
223
224#define PIXIS_VCLKH 0x19
225#define PIXIS_VCLKL 0x1A
226#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
227#define PIXIS_VSPEED2_TSEC1SER 0x8
228#define PIXIS_VSPEED2_TSEC2SER 0x4
229#define PIXIS_VSPEED2_TSEC3SER 0x2
230#define PIXIS_VSPEED2_TSEC4SER 0x1
231#define PIXIS_VCFGEN1_TSEC1SER 0x20
232#define PIXIS_VCFGEN1_TSEC2SER 0x20
233#define PIXIS_VCFGEN1_TSEC3SER 0x20
234#define PIXIS_VCFGEN1_TSEC4SER 0x20
235#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
236 | PIXIS_VSPEED2_TSEC2SER \
237 | PIXIS_VSPEED2_TSEC3SER \
238 | PIXIS_VSPEED2_TSEC4SER)
239#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
240 | PIXIS_VCFGEN1_TSEC2SER \
241 | PIXIS_VCFGEN1_TSEC3SER \
242 | PIXIS_VCFGEN1_TSEC4SER)
243
244#define CONFIG_SYS_INIT_RAM_LOCK 1
245#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
246#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
247
248#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
249#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
250
251#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
252#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
253
254#ifndef CONFIG_NAND_SPL
255#define CONFIG_SYS_NAND_BASE 0xffa00000
256#ifdef CONFIG_PHYS_64BIT
257#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
258#else
259#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
260#endif
261#else
262#define CONFIG_SYS_NAND_BASE 0xfff00000
263#ifdef CONFIG_PHYS_64BIT
264#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
265#else
266#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
267#endif
268#endif
269
270#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
271 CONFIG_SYS_NAND_BASE + 0x40000, \
272 CONFIG_SYS_NAND_BASE + 0x80000,\
273 CONFIG_SYS_NAND_BASE + 0xC0000}
274#define CONFIG_SYS_MAX_NAND_DEVICE 4
275#define CONFIG_NAND_FSL_ELBC 1
276#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
277#define CONFIG_SYS_NAND_MAX_OOBFREE 5
278#define CONFIG_SYS_NAND_MAX_ECCPOS 56
279
280
281#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
282#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
283#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
284#define CONFIG_SYS_NAND_U_BOOT_START \
285 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
286#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
287#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
288#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
289
290
291#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
292 | (2<<BR_DECC_SHIFT) \
293 | BR_PS_8 \
294 | BR_MS_FCM \
295 | BR_V)
296#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
297 | OR_FCM_PGS \
298 | OR_FCM_CSCT \
299 | OR_FCM_CST \
300 | OR_FCM_CHT \
301 | OR_FCM_SCY_1 \
302 | OR_FCM_TRLX \
303 | OR_FCM_EHTR)
304
305#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
306#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
307#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
308#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
309#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
310 | (2<<BR_DECC_SHIFT) \
311 | BR_PS_8 \
312 | BR_MS_FCM \
313 | BR_V)
314#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM
315#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
316 | (2<<BR_DECC_SHIFT) \
317 | BR_PS_8 \
318 | BR_MS_FCM \
319 | BR_V)
320#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM
321
322#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
323 | (2<<BR_DECC_SHIFT) \
324 | BR_PS_8 \
325 | BR_MS_FCM \
326 | BR_V)
327#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM
328
329
330
331
332
333#define CONFIG_SYS_NS16550_SERIAL
334#define CONFIG_SYS_NS16550_REG_SIZE 1
335#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
336#ifdef CONFIG_NAND_SPL
337#define CONFIG_NS16550_MIN_FUNCTIONS
338#endif
339
340#define CONFIG_SYS_BAUDRATE_TABLE \
341 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
342
343#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
344#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
345
346
347#define CONFIG_SYS_I2C
348#define CONFIG_SYS_I2C_FSL
349#define CONFIG_SYS_FSL_I2C_SPEED 400000
350#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
351#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
352#define CONFIG_SYS_FSL_I2C2_SPEED 400000
353#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
354#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
355#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
356#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
357
358
359
360
361#define CONFIG_ID_EEPROM
362#ifdef CONFIG_ID_EEPROM
363#define CONFIG_SYS_I2C_EEPROM_NXID
364#endif
365#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
366#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
367#define CONFIG_SYS_EEPROM_BUS_NUM 1
368
369
370
371
372
373
374
375#define CONFIG_SYS_PCIE3_NAME "ULI"
376#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
377#ifdef CONFIG_PHYS_64BIT
378#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
379#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
380#else
381#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
382#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
383#endif
384#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
385#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
386#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
387#ifdef CONFIG_PHYS_64BIT
388#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
389#else
390#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
391#endif
392#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
393
394
395#define CONFIG_SYS_PCIE2_NAME "Slot 1"
396#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
397#ifdef CONFIG_PHYS_64BIT
398#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
399#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
400#else
401#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
402#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
403#endif
404#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
405#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
406#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
407#ifdef CONFIG_PHYS_64BIT
408#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
409#else
410#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
411#endif
412#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
413
414
415#define CONFIG_SYS_PCIE1_NAME "Slot 2"
416#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
417#ifdef CONFIG_PHYS_64BIT
418#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
419#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
420#else
421#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
422#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
423#endif
424#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
425#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
426#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
427#ifdef CONFIG_PHYS_64BIT
428#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
429#else
430#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
431#endif
432#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
433
434#if defined(CONFIG_PCI)
435
436
437#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
438
439
440
441#if defined(CONFIG_VIDEO)
442#define CONFIG_BIOSEMU
443#define CONFIG_ATI_RADEON_FB
444#define CONFIG_VIDEO_LOGO
445#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
446#endif
447
448#undef CONFIG_EEPRO100
449#undef CONFIG_TULIP
450
451#ifndef CONFIG_PCI_PNP
452 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
453 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
454 #define PCI_IDSEL_NUMBER 0x11
455#endif
456
457#define CONFIG_PCI_SCAN_SHOW
458
459#ifdef CONFIG_SCSI_AHCI
460#define CONFIG_SATA_ULI5288
461#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
462#define CONFIG_SYS_SCSI_MAX_LUN 1
463#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
464#endif
465
466#endif
467
468#if defined(CONFIG_TSEC_ENET)
469
470#define CONFIG_MII_DEFAULT_TSEC 1
471#define CONFIG_TSEC1 1
472#define CONFIG_TSEC1_NAME "eTSEC1"
473#define CONFIG_TSEC2 1
474#define CONFIG_TSEC2_NAME "eTSEC2"
475#define CONFIG_TSEC3 1
476#define CONFIG_TSEC3_NAME "eTSEC3"
477#define CONFIG_TSEC4 1
478#define CONFIG_TSEC4_NAME "eTSEC4"
479
480#define CONFIG_PIXIS_SGMII_CMD
481#define CONFIG_FSL_SGMII_RISER 1
482#define SGMII_RISER_PHY_OFFSET 0x1c
483
484#ifdef CONFIG_FSL_SGMII_RISER
485#define CONFIG_SYS_TBIPA_VALUE 0x10
486#endif
487
488#define TSEC1_PHY_ADDR 0
489#define TSEC2_PHY_ADDR 1
490#define TSEC3_PHY_ADDR 2
491#define TSEC4_PHY_ADDR 3
492
493#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
494#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
495#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
496#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
497
498#define TSEC1_PHYIDX 0
499#define TSEC2_PHYIDX 0
500#define TSEC3_PHYIDX 0
501#define TSEC4_PHYIDX 0
502
503#define CONFIG_ETHPRIME "eTSEC1"
504#endif
505
506
507
508
509
510#if defined(CONFIG_SYS_RAMBOOT)
511
512#else
513 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
514 #define CONFIG_ENV_ADDR 0xfff80000
515 #else
516 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
517 #endif
518 #define CONFIG_ENV_SIZE 0x2000
519 #define CONFIG_ENV_SECT_SIZE 0x20000
520#endif
521
522#define CONFIG_LOADS_ECHO 1
523#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
524
525
526
527
528
529#ifdef CONFIG_USB_EHCI_HCD
530#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
531#define CONFIG_PCI_EHCI_DEVICE 0
532#endif
533
534#undef CONFIG_WATCHDOG
535
536
537
538
539#define CONFIG_SYS_LOAD_ADDR 0x2000000
540
541
542
543
544
545
546#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
547#define CONFIG_SYS_BOOTM_LEN (64 << 20)
548
549#if defined(CONFIG_CMD_KGDB)
550#define CONFIG_KGDB_BAUDRATE 230400
551#endif
552
553
554
555
556#if defined(CONFIG_TSEC_ENET)
557#define CONFIG_HAS_ETH0
558#define CONFIG_HAS_ETH1
559#define CONFIG_HAS_ETH2
560#define CONFIG_HAS_ETH3
561#endif
562
563#define CONFIG_IPADDR 192.168.1.254
564
565#define CONFIG_HOSTNAME "unknown"
566#define CONFIG_ROOTPATH "/opt/nfsroot"
567#define CONFIG_BOOTFILE "uImage"
568#define CONFIG_UBOOTPATH u-boot.bin
569
570#define CONFIG_SERVERIP 192.168.1.1
571#define CONFIG_GATEWAYIP 192.168.1.1
572#define CONFIG_NETMASK 255.255.255.0
573
574
575#define CONFIG_LOADADDR 1000000
576
577#define CONFIG_EXTRA_ENV_SETTINGS \
578"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
579"netdev=eth0\0" \
580"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
581"tftpflash=tftpboot $loadaddr $uboot; " \
582 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
583 " +$filesize; " \
584 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
585 " +$filesize; " \
586 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
587 " $filesize; " \
588 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
589 " +$filesize; " \
590 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
591 " $filesize\0" \
592"consoledev=ttyS0\0" \
593"ramdiskaddr=2000000\0" \
594"ramdiskfile=8572ds/ramdisk.uboot\0" \
595"fdtaddr=1e00000\0" \
596"fdtfile=8572ds/mpc8572ds.dtb\0" \
597"bdev=sda3\0"
598
599#define CONFIG_HDBOOT \
600 "setenv bootargs root=/dev/$bdev rw " \
601 "console=$consoledev,$baudrate $othbootargs;" \
602 "tftp $loadaddr $bootfile;" \
603 "tftp $fdtaddr $fdtfile;" \
604 "bootm $loadaddr - $fdtaddr"
605
606#define CONFIG_NFSBOOTCOMMAND \
607 "setenv bootargs root=/dev/nfs rw " \
608 "nfsroot=$serverip:$rootpath " \
609 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
610 "console=$consoledev,$baudrate $othbootargs;" \
611 "tftp $loadaddr $bootfile;" \
612 "tftp $fdtaddr $fdtfile;" \
613 "bootm $loadaddr - $fdtaddr"
614
615#define CONFIG_RAMBOOTCOMMAND \
616 "setenv bootargs root=/dev/ram rw " \
617 "console=$consoledev,$baudrate $othbootargs;" \
618 "tftp $ramdiskaddr $ramdiskfile;" \
619 "tftp $loadaddr $bootfile;" \
620 "tftp $fdtaddr $fdtfile;" \
621 "bootm $loadaddr $ramdiskaddr $fdtaddr"
622
623#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
624
625#endif
626