1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 4 * 5 * Based on original Kirkwood support which is 6 * (C) Copyright 2009 7 * Marvell Semiconductor <www.marvell.com> 8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 */ 10 11#ifndef _CONFIG_EDMINIV2_H 12#define _CONFIG_EDMINIV2_H 13 14/* 15 * SPL 16 */ 17 18#define CONFIG_SPL_TEXT_BASE 0xffff0000 19#define CONFIG_SPL_MAX_SIZE 0x0000fff0 20#define CONFIG_SPL_STACK 0x00020000 21#define CONFIG_SPL_BSS_START_ADDR 0x00020000 22#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 23#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 24#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 25#define CONFIG_SYS_UBOOT_BASE 0xfff90000 26#define CONFIG_SYS_UBOOT_START 0x00800000 27 28/* 29 * High Level Configuration Options (easy to change) 30 */ 31 32#define CONFIG_FEROCEON 1 /* CPU Core subversion */ 33#define CONFIG_88F5182 1 /* SOC Name */ 34 35#include <asm/arch/orion5x.h> 36/* 37 * CLKs configurations 38 */ 39 40/* 41 * Board-specific values for Orion5x MPP low level init: 42 * - MPPs 12 to 15 are SATA LEDs (mode 5) 43 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 44 * MPP16 to MPP19, mode 0 for others 45 */ 46 47#define ORION5X_MPP0_7 0x00000003 48#define ORION5X_MPP8_15 0x55550000 49#define ORION5X_MPP16_23 0x00005555 50 51/* 52 * Board-specific values for Orion5x GPIO low level init: 53 * - GPIO3 is input (RTC interrupt) 54 * - GPIO16 is Power LED control (0 = on, 1 = off) 55 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 56 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 57 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 58 * - GPIO22 is SATA disk power status () 59 * - GPIO23 is supply status for SATA disk () 60 * - GPIO24 is supply control for board (write 1 to power off) 61 * Last GPIO is 25, further bits are supposed to be 0. 62 * Enable mask has ones for INPUT, 0 for OUTPUT. 63 * Default is LED ON, board ON :) 64 */ 65 66#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 67#define ORION5X_GPIO_OUT_VALUE 0x00000000 68#define ORION5X_GPIO_IN_POLARITY 0x000000d0 69 70/* 71 * NS16550 Configuration 72 */ 73 74#define CONFIG_SYS_NS16550_SERIAL 75#define CONFIG_SYS_NS16550_REG_SIZE (-4) 76#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 77#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 78 79/* 80 * Serial Port configuration 81 * The following definitions let you select what serial you want to use 82 * for your console driver. 83 */ 84 85#define CONFIG_SYS_BAUDRATE_TABLE \ 86 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 87 88/* 89 * FLASH configuration 90 */ 91 92#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 93#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 94#define CONFIG_SYS_FLASH_BASE 0xfff80000 95 96/* auto boot */ 97 98/* 99 * For booting Linux, the board info and command line data 100 * have to be in the first 8 MB of memory, since this is 101 * the maximum mapped by the Linux kernel during initialization. 102 */ 103#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 104#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 105#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 106 107#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 108/* 109 * Commands configuration 110 */ 111 112/* 113 * Network 114 */ 115 116#ifdef CONFIG_CMD_NET 117#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 118#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 119#define CONFIG_PHY_BASE_ADR 0x8 120#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 121#define CONFIG_NETCONSOLE /* include NetConsole support */ 122#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 123#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 124#endif 125 126/* 127 * IDE 128 */ 129#ifdef CONFIG_IDE 130#define __io 131#define CONFIG_IDE_PREINIT 132/* ED Mini V has an IDE-compatible SATA connector for port 1 */ 133#define CONFIG_MVSATA_IDE_USE_PORT1 134/* Needs byte-swapping for ATA data register */ 135#define CONFIG_IDE_SWAP_IO 136/* Data, registers and alternate blocks are at the same offset */ 137#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 138#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 139#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 140/* Each 8-bit ATA register is aligned to a 4-bytes address */ 141#define CONFIG_SYS_ATA_STRIDE 4 142/* Controller supports 48-bits LBA addressing */ 143#define CONFIG_LBA48 144/* A single bus, a single device */ 145#define CONFIG_SYS_IDE_MAXBUS 1 146#define CONFIG_SYS_IDE_MAXDEVICE 1 147/* ATA registers base is at SATA controller base */ 148#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 149/* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 150#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 151/* end of IDE defines */ 152#endif /* CMD_IDE */ 153 154/* 155 * Common USB/EHCI configuration 156 */ 157#ifdef CONFIG_CMD_USB 158#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 159#endif /* CONFIG_CMD_USB */ 160 161/* 162 * I2C related stuff 163 */ 164#ifdef CONFIG_CMD_I2C 165#define CONFIG_SYS_I2C 166#define CONFIG_SYS_I2C_MVTWSI 167#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 168#define CONFIG_SYS_I2C_SLAVE 0x0 169#define CONFIG_SYS_I2C_SPEED 100000 170#endif 171 172/* 173 * Environment variables configurations 174 */ 175#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 176#define CONFIG_ENV_SIZE 0x2000 177#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 178 179/* 180 * Size of malloc() pool 181 */ 182#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 183 184/* 185 * Other required minimal configurations 186 */ 187#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 188 189#define CONFIG_SYS_LOAD_ADDR 0x00800000 190#define CONFIG_SYS_MEMTEST_START 0x00400000 191#define CONFIG_SYS_MEMTEST_END 0x007fffff 192#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 193 194/* Enable command line editing */ 195 196/* provide extensive help */ 197 198/* additions for new relocation code, must be added to all boards */ 199#define CONFIG_SYS_SDRAM_BASE 0 200#define CONFIG_SYS_INIT_SP_ADDR \ 201 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 202 203#endif /* _CONFIG_EDMINIV2_H */ 204