1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6#ifndef __CONFIG_H 7#define __CONFIG_H 8 9#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 10 11#define CONFIG_SYS_FSL_CLK 12 13/* 14 * Size of malloc() pool 15 */ 16#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 17 18#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 19#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 20 21#define CONFIG_SYS_CLK_FREQ 100000000 22#define CONFIG_DDR_CLK_FREQ 100000000 23 24/* 25 * DDR: 800 MHz ( 1600 MT/s data rate ) 26 */ 27 28#define DDR_SDRAM_CFG 0x470c0008 29#define DDR_CS0_BNDS 0x008000bf 30#define DDR_CS0_CONFIG 0x80014302 31#define DDR_TIMING_CFG_0 0x50550004 32#define DDR_TIMING_CFG_1 0xbcb38c56 33#define DDR_TIMING_CFG_2 0x0040d120 34#define DDR_TIMING_CFG_3 0x010e1000 35#define DDR_TIMING_CFG_4 0x00000001 36#define DDR_TIMING_CFG_5 0x03401400 37#define DDR_SDRAM_CFG_2 0x00401010 38#define DDR_SDRAM_MODE 0x00061c60 39#define DDR_SDRAM_MODE_2 0x00180000 40#define DDR_SDRAM_INTERVAL 0x18600618 41#define DDR_DDR_WRLVL_CNTL 0x8655f605 42#define DDR_DDR_WRLVL_CNTL_2 0x05060607 43#define DDR_DDR_WRLVL_CNTL_3 0x05050505 44#define DDR_DDR_CDR1 0x80040000 45#define DDR_DDR_CDR2 0x00000001 46#define DDR_SDRAM_CLK_CNTL 0x02000000 47#define DDR_DDR_ZQ_CNTL 0x89080600 48#define DDR_CS0_CONFIG_2 0 49#define DDR_SDRAM_CFG_MEM_EN 0x80000000 50#define SDRAM_CFG2_D_INIT 0x00000010 51#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 52#define SDRAM_CFG2_FRC_SR 0x80000000 53#define SDRAM_CFG_BI 0x00000001 54 55#ifdef CONFIG_RAMBOOT_PBL 56#define CONFIG_SYS_FSL_PBL_PBI \ 57 board/freescale/ls1021aiot/ls102xa_pbi.cfg 58#endif 59 60#ifdef CONFIG_SD_BOOT 61#define CONFIG_SYS_FSL_PBL_RCW \ 62 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 63#define CONFIG_SPL_LIBCOMMON_SUPPORT 64#define CONFIG_SPL_LIBGENERIC_SUPPORT 65#define CONFIG_SPL_ENV_SUPPORT 66#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 67#define CONFIG_SPL_I2C_SUPPORT 68#define CONFIG_SPL_WATCHDOG_SUPPORT 69#define CONFIG_SPL_MMC_SUPPORT 70#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 71 72#define CONFIG_SPL_TEXT_BASE 0x10000000 73#define CONFIG_SPL_MAX_SIZE 0x1a000 74#define CONFIG_SPL_STACK 0x1001d000 75#define CONFIG_SPL_PAD_TO 0x1c000 76 77#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 78 CONFIG_SYS_MONITOR_LEN) 79#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 80#define CONFIG_SPL_BSS_START_ADDR 0x80100000 81#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 82#define CONFIG_SYS_MONITOR_LEN 0x80000 83#endif 84 85#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 86#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 87 88#define CONFIG_CHIP_SELECTS_PER_CTRL 4 89 90/* 91 * Serial Port 92 */ 93#define CONFIG_SYS_NS16550_SERIAL 94#define CONFIG_SYS_NS16550_REG_SIZE 1 95#define CONFIG_SYS_NS16550_CLK get_serial_clock() 96 97/* 98 * I2C 99 */ 100#define CONFIG_CMD_I2C 101#define CONFIG_SYS_I2C 102#define CONFIG_SYS_I2C_MXC 103#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 104#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 105#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 106 107/* EEPROM */ 108#define CONFIG_ID_EEPROM 109#define CONFIG_SYS_I2C_EEPROM_NXID 110#define CONFIG_SYS_EEPROM_BUS_NUM 0 111#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 112#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 113 114/* 115 * MMC 116 */ 117#define CONFIG_CMD_MMC 118 119/* SATA */ 120#define CONFIG_SCSI_AHCI_PLAT 121#ifndef PCI_DEVICE_ID_FREESCALE_AHCI 122#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 123#endif 124#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 125 PCI_DEVICE_ID_FREESCALE_AHCI} 126 127#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 128#define CONFIG_SYS_SCSI_MAX_LUN 1 129#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 130 CONFIG_SYS_SCSI_MAX_LUN) 131 132/* SPI */ 133#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 134#define CONFIG_SPI_FLASH_SPANSION 135 136/* QSPI */ 137#define QSPI0_AMBA_BASE 0x40000000 138#define FSL_QSPI_FLASH_SIZE (1 << 24) 139#define FSL_QSPI_FLASH_NUM 2 140#define CONFIG_SPI_FLASH_SPANSION 141#endif 142 143/* DM SPI */ 144#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 145#define CONFIG_CMD_SF 146#define CONFIG_DM_SPI_FLASH 147#endif 148 149/* 150 * eTSEC 151 */ 152 153#ifdef CONFIG_TSEC_ENET 154#define CONFIG_MII_DEFAULT_TSEC 1 155#define CONFIG_TSEC1 1 156#define CONFIG_TSEC1_NAME "eTSEC1" 157#define CONFIG_TSEC2 1 158#define CONFIG_TSEC2_NAME "eTSEC2" 159 160#define TSEC1_PHY_ADDR 1 161#define TSEC2_PHY_ADDR 3 162 163#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 164#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 165 166#define TSEC1_PHYIDX 0 167#define TSEC2_PHYIDX 0 168 169#define CONFIG_ETHPRIME "eTSEC2" 170 171#define CONFIG_PHY_ATHEROS 172 173#define CONFIG_HAS_ETH0 174#define CONFIG_HAS_ETH1 175#define CONFIG_HAS_ETH2 176#endif 177 178/* PCIe */ 179#define CONFIG_PCIE1 /* PCIE controler 1 */ 180#define CONFIG_PCIE2 /* PCIE controler 2 */ 181 182#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 183 184#ifdef CONFIG_PCI 185#define CONFIG_PCI_SCAN_SHOW 186#endif 187 188#define CONFIG_CMD_MII 189 190#define CONFIG_CMDLINE_TAG 191 192#define CONFIG_PEN_ADDR_BIG_ENDIAN 193#define CONFIG_LAYERSCAPE_NS_ACCESS 194#define CONFIG_SMP_PEN_ADDR 0x01ee0200 195#define COUNTER_FREQUENCY 12500000 196 197#define CONFIG_HWCONFIG 198#define HWCONFIG_BUFFER_SIZE 256 199 200#define CONFIG_FSL_DEVICE_DISABLE 201 202#define CONFIG_EXTRA_ENV_SETTINGS \ 203 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 204"initrd_high=0xffffffff\0" \ 205"fdt_high=0xffffffff\0" 206 207/* 208 * Miscellaneous configurable options 209 */ 210#define CONFIG_CMD_GREPENV 211#define CONFIG_CMD_MEMINFO 212 213#define CONFIG_SYS_LOAD_ADDR 0x82000000 214 215#define CONFIG_LS102XA_STREAM_ID 216 217#define CONFIG_SYS_INIT_SP_OFFSET \ 218 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 219#define CONFIG_SYS_INIT_SP_ADDR \ 220 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 221 222#ifdef CONFIG_SPL_BUILD 223#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 224#else 225/* start of monitor */ 226#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 227#endif 228 229#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 230 231/* 232 * Environment 233 */ 234 235#define CONFIG_ENV_OVERWRITE 236 237#if defined(CONFIG_SD_BOOT) 238#define CONFIG_ENV_OFFSET 0x100000 239#define CONFIG_SYS_MMC_ENV_DEV 0 240#define CONFIG_ENV_SIZE 0x2000 241#elif defined(CONFIG_QSPI_BOOT) 242#define CONFIG_ENV_SIZE 0x2000 243#define CONFIG_ENV_OFFSET 0x100000 244#define CONFIG_ENV_SECT_SIZE 0x10000 245#endif 246 247#define CONFIG_OF_BOARD_SETUP 248#define CONFIG_OF_STDOUT_VIA_ALIAS 249 250#include <asm/fsl_secure_boot.h> 251 252#endif 253