1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2017-2018 NXP 4 */ 5 6#ifndef __LS1088_COMMON_H 7#define __LS1088_COMMON_H 8 9/* SPL build */ 10#ifdef CONFIG_SPL_BUILD 11#define SPL_NO_BOARDINFO 12#define SPL_NO_QIXIS 13#define SPL_NO_PCI 14#define SPL_NO_ENV 15#define SPL_NO_RTC 16#define SPL_NO_USB 17#define SPL_NO_SATA 18#define SPL_NO_QSPI 19#define SPL_NO_IFC 20#undef CONFIG_DISPLAY_CPUINFO 21#endif 22 23#define CONFIG_REMAKE_ELF 24 25#include <asm/arch/stream_id_lsch3.h> 26#include <asm/arch/config.h> 27#include <asm/arch/soc.h> 28 29#define LS1088ARDB_PB_BOARD 0x4A 30/* Link Definitions */ 31#ifdef CONFIG_TFABOOT 32#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 33#else 34#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 35#endif 36 37/* Link Definitions */ 38#ifdef CONFIG_TFABOOT 39#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 40#else 41#ifdef CONFIG_QSPI_BOOT 42#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 43#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 44#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ 45 CONFIG_ENV_OFFSET) 46#endif 47#endif 48 49#define CONFIG_SKIP_LOWLEVEL_INIT 50 51#define CONFIG_VERY_BIG_RAM 52#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 53#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 54#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 55#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 56#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 57/* 58 * SMP Definitinos 59 */ 60#define CPU_RELEASE_ADDR secondary_boot_func 61 62#ifdef CONFIG_PCI 63#define CONFIG_CMD_PCI 64#endif 65 66/* Size of malloc() pool */ 67#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 68 69/* I2C */ 70#define CONFIG_SYS_I2C 71 72/* Serial Port */ 73#define CONFIG_SYS_NS16550_SERIAL 74#define CONFIG_SYS_NS16550_REG_SIZE 1 75#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) 76 77#define CONFIG_BAUDRATE 115200 78#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 79 80#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) 81/* IFC */ 82#define CONFIG_FSL_IFC 83#endif 84 85/* 86 * During booting, IFC is mapped at the region of 0x30000000. 87 * But this region is limited to 256MB. To accommodate NOR, promjet 88 * and FPGA. This region is divided as below: 89 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 90 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 91 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 92 * 93 * To accommodate bigger NOR flash and other devices, we will map IFC 94 * chip selects to as below: 95 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 96 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 97 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 98 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 99 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 100 * 101 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 102 * CONFIG_SYS_FLASH_BASE has the final address (core view) 103 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 104 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 105 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 106 */ 107 108#define CONFIG_SYS_FLASH_BASE 0x580000000ULL 109#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 110#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 111 112#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 113#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 114 115#ifndef __ASSEMBLY__ 116unsigned long long get_qixis_addr(void); 117#endif 118 119#define QIXIS_BASE get_qixis_addr() 120#define QIXIS_BASE_PHYS 0x20000000 121#define QIXIS_BASE_PHYS_EARLY 0xC000000 122 123 124#define CONFIG_SYS_NAND_BASE 0x530000000ULL 125#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 126 127 128/* MC firmware */ 129/* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 130#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 131#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 132#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 133#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 134#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 135#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 136 137/* Define phy_reset function to boot the MC based on mcinitcmd. 138 * This happens late enough to properly fixup u-boot env MAC addresses. 139 */ 140#define CONFIG_RESET_PHY_R 141 142/* 143 * Carve out a DDR region which will not be used by u-boot/Linux 144 * 145 * It will be used by MC and Debug Server. The MC region must be 146 * 512MB aligned, so the min size to hide is 512MB. 147 */ 148 149#if defined(CONFIG_FSL_MC_ENET) 150#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) 151#endif 152/* Command line configuration */ 153#define CONFIG_CMD_CACHE 154 155/* Miscellaneous configurable options */ 156#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 157 158/* SATA */ 159#ifdef CONFIG_SCSI 160#define CONFIG_SCSI_AHCI_PLAT 161#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 162 163#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 164#define CONFIG_SYS_SCSI_MAX_LUN 1 165#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 166 CONFIG_SYS_SCSI_MAX_LUN) 167#endif 168 169/* Physical Memory Map */ 170#define CONFIG_CHIP_SELECTS_PER_CTRL 4 171 172#define CONFIG_HWCONFIG 173#define HWCONFIG_BUFFER_SIZE 128 174 175/* #define CONFIG_DISPLAY_CPUINFO */ 176 177#ifndef SPL_NO_ENV 178/* Allow to overwrite serial and ethaddr */ 179#define CONFIG_ENV_OVERWRITE 180 181/* Initial environment variables */ 182#define CONFIG_EXTRA_ENV_SETTINGS \ 183 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 184 "loadaddr=0x80100000\0" \ 185 "kernel_addr=0x100000\0" \ 186 "ramdisk_addr=0x800000\0" \ 187 "ramdisk_size=0x2000000\0" \ 188 "fdt_high=0xa0000000\0" \ 189 "initrd_high=0xffffffffffffffff\0" \ 190 "kernel_start=0x581000000\0" \ 191 "kernel_load=0xa0000000\0" \ 192 "kernel_size=0x2800000\0" \ 193 "console=ttyAMA0,38400n8\0" \ 194 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 195 " 0x580e00000 \0" 196 197#ifndef CONFIG_TFABOOT 198#if defined(CONFIG_QSPI_BOOT) 199#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ 200 "sf read 0x80001000 0xd00000 0x100000;"\ 201 " fsl_mc lazyapply dpl 0x80001000 &&" \ 202 " sf read $kernel_load $kernel_start" \ 203 " $kernel_size && bootm $kernel_load" 204#elif defined(CONFIG_SD_BOOT) 205#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\ 206 " fsl_mc lazyapply dpl 0x80001000 &&" \ 207 " mmc read $kernel_load $kernel_start" \ 208 " $kernel_size && bootm $kernel_load" 209#else /* NOR BOOT*/ 210#define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \ 211 " cp.b $kernel_start $kernel_load" \ 212 " $kernel_size && bootm $kernel_load" 213#endif 214#endif /* CONFIG_TFABOOT */ 215#endif 216 217/* Monitor Command Prompt */ 218#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 219#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 220 sizeof(CONFIG_SYS_PROMPT) + 16) 221#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 222#define CONFIG_SYS_MAXARGS 64 /* max command args */ 223 224#ifdef CONFIG_SPL 225#define CONFIG_SPL_BSS_START_ADDR 0x80100000 226#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 227#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 228#define CONFIG_SPL_MAX_SIZE 0x16000 229#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 230#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 231#define CONFIG_SPL_TEXT_BASE 0x1800a000 232 233#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 234#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 235 236#ifdef CONFIG_SECURE_BOOT 237#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 238/* 239 * HDR would be appended at end of image and copied to DDR along 240 * with U-Boot image. Here u-boot max. size is 512K. So if binary 241 * size increases then increase this size in case of secure boot as 242 * it uses raw u-boot image instead of fit image. 243 */ 244#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 245#else 246#define CONFIG_SYS_MONITOR_LEN 0x100000 247#endif /* ifdef CONFIG_SECURE_BOOT */ 248 249#endif 250#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 251 252#endif /* __LS1088_COMMON_H */ 253