LXR uboot/include/configs/pm9g45.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2010
   4 * Ilko Iliev <iliev@ronetix.at>
   5 * Asen Dimov <dimov@ronetix.at>
   6 * Ronetix GmbH <www.ronetix.at>
   7 *
   8 * (C) Copyright 2007-2008
   9 * Stelian Pop <stelian@popies.net>
  10 * Lead Tech Design <www.leadtechdesign.com>
  11 *
  12 * Configuation settings for the PM9G45 board.
  13 */
  14
  15#ifndef __CONFIG_H
  16#define __CONFIG_H
  17
  18/*
  19 * SoC must be defined first, before hardware.h is included.
  20 * In this case SoC is defined in boards.cfg.
  21 */
  22#include <asm/hardware.h>
  23
  24#define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9G45"
  25
  26#define CONFIG_MACH_TYPE        MACH_TYPE_PM9G45
  27
  28/* ARM asynchronous clock */
  29#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  30#define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  31
  32#define CONFIG_ARCH_CPU_INIT
  33
  34#define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
  35#define CONFIG_SETUP_MEMORY_TAGS 1
  36#define CONFIG_INITRD_TAG       1
  37
  38#define CONFIG_SKIP_LOWLEVEL_INIT
  39
  40/*
  41 * Hardware drivers
  42 */
  43#define CONFIG_AT91_GPIO        1
  44#define CONFIG_ATMEL_USART      1
  45#define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  46#define CONFIG_USART_ID                 ATMEL_ID_SYS
  47
  48#define CONFIG_SYS_USE_NANDFLASH        1
  49
  50/* LED */
  51#define CONFIG_AT91_LED
  52#define CONFIG_RED_LED          GPIO_PIN_PD(31) /* this is the user1 led */
  53#define CONFIG_GREEN_LED        GPIO_PIN_PD(0)  /* this is the user2 led */
  54
  55
  56/*
  57 * BOOTP options
  58 */
  59#define CONFIG_BOOTP_BOOTFILESIZE       1
  60
  61#define CONFIG_JFFS2_CMDLINE            1
  62#define CONFIG_JFFS2_NAND               1
  63#define CONFIG_JFFS2_DEV                "nand0" /* NAND dev jffs2 lives on */
  64#define CONFIG_JFFS2_PART_OFFSET        0       /* start of jffs2 partition */
  65#define CONFIG_JFFS2_PART_SIZE          (256 * 1024 * 1024) /* partition */
  66
  67/* SDRAM */
  68#define PHYS_SDRAM                      0x70000000
  69#define PHYS_SDRAM_SIZE                 0x08000000      /* 128 megs */
  70
  71/* NAND flash */
  72#ifdef CONFIG_CMD_NAND
  73#define CONFIG_SYS_MAX_NAND_DEVICE      1
  74#define CONFIG_SYS_NAND_BASE            0x40000000
  75#define CONFIG_SYS_NAND_DBW_8           1
  76/* our ALE is AD21 */
  77#define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  78/* our CLE is AD22 */
  79#define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  80#define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
  81#define CONFIG_SYS_NAND_READY_PIN       GPIO_PIN_PD(3)
  82
  83#endif
  84
  85/* Ethernet */
  86#define CONFIG_MACB                     1
  87#define CONFIG_RMII                     1
  88#define CONFIG_NET_RETRY_COUNT          20
  89#define CONFIG_RESET_PHY_R              1
  90
  91/* USB */
  92#define CONFIG_USB_ATMEL
  93#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  94#define CONFIG_USB_OHCI_NEW             1
  95#define CONFIG_SYS_USB_OHCI_CPU_INIT    1
  96#define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00700000 /* _UHP_OHCI_BASE */
  97#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "at91sam9g45"
  98#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
  99
 100/* board specific(not enough SRAM) */
 101#define CONFIG_AT91SAM9G45_LCD_BASE     PHYS_SDRAM + 0xE00000
 102
 103#define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM + 0x2000000 /* load addr */
 104
 105#define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM
 106#define CONFIG_SYS_MEMTEST_END          CONFIG_AT91SAM9G45_LCD_BASE
 107
 108/* bootstrap + u-boot + env + linux in nandflash */
 109#define CONFIG_ENV_OFFSET               0x60000
 110#define CONFIG_ENV_OFFSET_REDUND        0x80000
 111#define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 112#define CONFIG_BOOTCOMMAND      "nand read 0x72000000 0x200000 0x200000; bootm"
 113
 114/*
 115 * Size of malloc() pool
 116 */
 117#define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
 118                                        0x1000)
 119
 120#define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 121#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 122                                GENERATED_GBL_DATA_SIZE)
 123
 124#endif
 125