uboot/include/configs/xpedite517x.h
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   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2009 Extreme Engineering Solutions, Inc.
   4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
   5 */
   6
   7/*
   8 * xpedite517x board configuration file
   9 */
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13/*
  14 * High Level Configuration Options
  15 */
  16#define CONFIG_SYS_BOARD_NAME   "XPedite5170"
  17#define CONFIG_SYS_FORM_3U_VPX  1
  18#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  19#define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  20#define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  21#define CONFIG_ALTIVEC          1
  22
  23#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  24#define CONFIG_PCIE1            1       /* PCIE controller 1 */
  25#define CONFIG_PCIE2            1       /* PCIE controller 2 */
  26#define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  27#define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  28#define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  29
  30/*
  31 * DDR config
  32 */
  33#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  34#define CONFIG_DDR_SPD
  35#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  36#define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  37#define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  38#define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  39#define CONFIG_DIMM_SLOTS_PER_CTLR      1
  40#define CONFIG_CHIP_SELECTS_PER_CTRL    1
  41#define CONFIG_DDR_ECC
  42#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  43#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  44#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  45#define CONFIG_VERY_BIG_RAM
  46#define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
  47
  48/*
  49 * virtual address to be used for temporary mappings.  There
  50 * should be 128k free at this VA.
  51 */
  52#define CONFIG_SYS_SCRATCH_VA   0xe0000000
  53
  54#ifndef __ASSEMBLY__
  55extern unsigned long get_board_sys_clk(unsigned long dummy);
  56#endif
  57
  58#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC86xx */
  59
  60/*
  61 * L2CR setup
  62 */
  63#define CONFIG_SYS_L2
  64#define L2_INIT         0
  65#define L2_ENABLE       (L2CR_L2E)
  66
  67/*
  68 * Base addresses -- Note these are effective addresses where the
  69 * actual resources get mapped (not physical addresses)
  70 */
  71#define CONFIG_SYS_CCSRBAR              0xef000000      /* relocated CCSRBAR */
  72#define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR
  73#define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  74#define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  75#define CONFIG_SYS_IMMR                 CONFIG_SYS_CCSRBAR
  76
  77/*
  78 * Diagnostics
  79 */
  80#define CONFIG_SYS_MEMTEST_START        0x10000000
  81#define CONFIG_SYS_MEMTEST_END          0x20000000
  82#define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY |\
  83                                         CONFIG_SYS_POST_I2C)
  84/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
  85#define I2C_ADDR_IGNORE_LIST            {0x50}
  86
  87/*
  88 * Memory map
  89 * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  90 * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
  91 * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
  92 * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
  93 * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
  94 * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
  95 * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
  96 * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
  97 * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
  98 * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
  99 */
 100
 101#define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_4 | LCRR_EADC_3)
 102
 103/*
 104 * NAND flash configuration
 105 */
 106#define CONFIG_SYS_NAND_BASE            0xef800000
 107#define CONFIG_SYS_NAND_BASE2           0xef840000      /* Unused at this time */
 108#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
 109#define CONFIG_SYS_MAX_NAND_DEVICE      2
 110#define CONFIG_NAND_ACTL
 111#define CONFIG_SYS_NAND_ACTL_ALE        (1 << 14)       /* C_LA14 */
 112#define CONFIG_SYS_NAND_ACTL_CLE        (1 << 15)       /* C_LA15 */
 113#define CONFIG_SYS_NAND_ACTL_NCE        0               /* NCE not controlled by ADDR */
 114#define CONFIG_SYS_NAND_ACTL_DELAY      25
 115#define CONFIG_JFFS2_NAND
 116
 117/*
 118 * NOR flash configuration
 119 */
 120#define CONFIG_SYS_FLASH_BASE           0xf8000000
 121#define CONFIG_SYS_FLASH_BASE2          0xf0000000
 122#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 123#define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 124#define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 125#define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 126#define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 127#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff00000, 0xc0000}, \
 128                                                  {0xf7f00000, 0xc0000} }
 129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 130#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 131
 132/*
 133 * Chip select configuration
 134 */
 135/* NOR Flash 0 on CS0 */
 136#define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  |\
 137                                 BR_PS_16               |\
 138                                 BR_V)
 139#define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            |\
 140                                 OR_GPCM_CSNT           |\
 141                                 OR_GPCM_XACS           |\
 142                                 OR_GPCM_ACS_DIV2       |\
 143                                 OR_GPCM_SCY_8          |\
 144                                 OR_GPCM_TRLX           |\
 145                                 OR_GPCM_EHTR           |\
 146                                 OR_GPCM_EAD)
 147
 148/* NOR Flash 1 on CS1 */
 149#define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 |\
 150                                 BR_PS_16               |\
 151                                 BR_V)
 152#define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 153
 154/* NAND flash on CS2 */
 155#define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   |\
 156                                 BR_PS_8                |\
 157                                 BR_V)
 158#define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB            |\
 159                                 OR_GPCM_BCTLD          |\
 160                                 OR_GPCM_CSNT           |\
 161                                 OR_GPCM_ACS_DIV4       |\
 162                                 OR_GPCM_SCY_4          |\
 163                                 OR_GPCM_TRLX           |\
 164                                 OR_GPCM_EHTR)
 165
 166/* Optional NAND flash on CS3 */
 167#define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  |\
 168                                 BR_PS_8                |\
 169                                 BR_V)
 170#define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 171
 172/*
 173 * Use L1 as initial stack
 174 */
 175#define CONFIG_SYS_INIT_RAM_LOCK        1
 176#define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 177#define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 178
 179#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 180#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 181
 182#define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 183#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 184
 185/*
 186 * Serial Port
 187 */
 188#define CONFIG_SYS_NS16550_SERIAL
 189#define CONFIG_SYS_NS16550_REG_SIZE     1
 190#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 191#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 192#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 193#define CONFIG_SYS_BAUDRATE_TABLE       \
 194        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 195#define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 196#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 197
 198/*
 199 * I2C
 200 */
 201#define CONFIG_SYS_I2C
 202#define CONFIG_SYS_I2C_FSL
 203#define CONFIG_SYS_FSL_I2C_SPEED        100000
 204#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 205#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 206#define CONFIG_SYS_FSL_I2C2_SPEED       100000
 207#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 208#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 209
 210/* PEX8518 slave I2C interface */
 211#define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 212
 213/* I2C DS1631 temperature sensor */
 214#define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 215
 216/* I2C EEPROM - AT24C128B */
 217#define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 218#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 219#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 220#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 221
 222/* I2C RTC */
 223#define CONFIG_RTC_M41T11               1
 224#define CONFIG_SYS_I2C_RTC_ADDR         0x68
 225#define CONFIG_SYS_M41T11_BASE_YEAR     2000
 226
 227/* GPIO */
 228#define CONFIG_PCA953X
 229#define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 230#define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 231#define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 232#define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 233#define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 234#define CONFIG_SYS_I2C_PCA9553_ADDR     0x62
 235
 236/*
 237 * PU = pulled high, PD = pulled low
 238 * I = input, O = output, IO = input/output
 239 */
 240/* PCA9557 @ 0x18*/
 241#define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 242#define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 243#define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 244#define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 245#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 246#define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 247
 248/* PCA9557 @ 0x1c*/
 249#define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 250#define CONFIG_SYS_PCA953X_PLUG_GPIO0           0x02 /* Samtec connector GPIO */
 251#define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 252#define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 253#define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 254#define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 255#define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 256#define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 257
 258/* PCA9557 @ 0x1e*/
 259#define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 260#define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 261#define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 262#define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 263#define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 264#define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; VPX Geographical address parity */
 265#define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; VPX P1 SYSCON */
 266
 267/* PCA9557 @ 0x1f */
 268#define CONFIG_SYS_PCA953X_VPX_GPIO0            0x01 /* PU; VPX P15 GPIO */
 269#define CONFIG_SYS_PCA953X_VPX_GPIO1            0x02 /* PU; VPX P15 GPIO */
 270#define CONFIG_SYS_PCA953X_VPX_GPIO2            0x04 /* PU; VPX P15 GPIO */
 271#define CONFIG_SYS_PCA953X_VPX_GPIO3            0x08 /* PU; VPX P15 GPIO */
 272
 273/*
 274 * General PCI
 275 * Memory space is mapped 1-1, but I/O space must start from 0.
 276 */
 277/* PCIE1 - PEX8518 */
 278#define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 279#define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 280#define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 281#define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 282#define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 283#define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 284
 285/* PCIE2 - VPX P1 */
 286#define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 287#define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 288#define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 289#define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 290#define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 291#define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 292
 293/*
 294 * Networking options
 295 */
 296#define CONFIG_ETHPRIME         "eTSEC1"
 297
 298#define CONFIG_TSEC1            1
 299#define CONFIG_TSEC1_NAME       "eTSEC1"
 300#define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 301#define TSEC1_PHY_ADDR          1
 302#define TSEC1_PHYIDX            0
 303#define CONFIG_HAS_ETH0
 304
 305#define CONFIG_TSEC2            1
 306#define CONFIG_TSEC2_NAME       "eTSEC2"
 307#define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 308#define TSEC2_PHY_ADDR          2
 309#define TSEC2_PHYIDX            0
 310#define CONFIG_HAS_ETH1
 311
 312/*
 313 * BAT mappings
 314 */
 315#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 316#define CONFIG_SYS_CCSR_DEFAULT_DBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 317                                         BATL_PP_RW                     |\
 318                                         BATL_CACHEINHIBIT              |\
 319                                         BATL_GUARDEDSTORAGE)
 320#define CONFIG_SYS_CCSR_DEFAULT_DBATU   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 321                                         BATU_BL_1M                     |\
 322                                         BATU_VS                        |\
 323                                         BATU_VP)
 324#define CONFIG_SYS_CCSR_DEFAULT_IBATL   (CONFIG_SYS_CCSRBAR_DEFAULT     |\
 325                                         BATL_PP_RW                     |\
 326                                         BATL_CACHEINHIBIT)
 327#define CONFIG_SYS_CCSR_DEFAULT_IBATU   CONFIG_SYS_CCSR_DEFAULT_DBATU
 328#endif
 329
 330/*
 331 * BAT0         2G      Cacheable, non-guarded
 332 * 0x0000_0000  2G      DDR
 333 */
 334#define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 335#define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 336#define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 337#define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 338
 339/*
 340 * BAT1         1G      Cache-inhibited, guarded
 341 * 0x8000_0000  1G      PCI-Express 1 Memory
 342 */
 343#define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 344                                 BATL_PP_RW                     |\
 345                                 BATL_CACHEINHIBIT              |\
 346                                 BATL_GUARDEDSTORAGE)
 347#define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 348                                 BATU_BL_1G                     |\
 349                                 BATU_VS                        |\
 350                                 BATU_VP)
 351#define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS      |\
 352                                 BATL_PP_RW                     |\
 353                                 BATL_CACHEINHIBIT)
 354#define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 355
 356/*
 357 * BAT2         512M    Cache-inhibited, guarded
 358 * 0xc000_0000  512M    PCI-Express 2 Memory
 359 */
 360#define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 361                                 BATL_PP_RW                     |\
 362                                 BATL_CACHEINHIBIT              |\
 363                                 BATL_GUARDEDSTORAGE)
 364#define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 365                                 BATU_BL_512M                   |\
 366                                 BATU_VS                        |\
 367                                 BATU_VP)
 368#define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCIE2_MEM_PHYS      |\
 369                                 BATL_PP_RW                     |\
 370                                 BATL_CACHEINHIBIT)
 371#define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 372
 373/*
 374 * BAT3         1M      Cache-inhibited, guarded
 375 * 0xe000_0000  1M      CCSR
 376 */
 377#define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR             |\
 378                                 BATL_PP_RW                     |\
 379                                 BATL_CACHEINHIBIT              |\
 380                                 BATL_GUARDEDSTORAGE)
 381#define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR             |\
 382                                 BATU_BL_1M                     |\
 383                                 BATU_VS                        |\
 384                                 BATU_VP)
 385#define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR             |\
 386                                 BATL_PP_RW                     |\
 387                                 BATL_CACHEINHIBIT)
 388#define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 389
 390/*
 391 * BAT4         32M     Cache-inhibited, guarded
 392 * 0xe200_0000  16M     PCI-Express 1 I/O
 393 * 0xe300_0000  16M     PCI-Express 2 I/0
 394 */
 395#define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 396                                 BATL_PP_RW                     |\
 397                                 BATL_CACHEINHIBIT              |\
 398                                 BATL_GUARDEDSTORAGE)
 399#define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 400                                 BATU_BL_32M                    |\
 401                                 BATU_VS                        |\
 402                                 BATU_VP)
 403#define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS       |\
 404                                 BATL_PP_RW                     |\
 405                                 BATL_CACHEINHIBIT)
 406#define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 407
 408/*
 409 * BAT5         128K    Cacheable, non-guarded
 410 * 0xe400_1000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 411 */
 412#define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR       |\
 413                                 BATL_PP_RW                     |\
 414                                 BATL_MEMCOHERENCE)
 415#define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR       |\
 416                                 BATU_BL_128K                   |\
 417                                 BATU_VS                        |\
 418                                 BATU_VP)
 419#define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 420#define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 421
 422/*
 423 * BAT6         256M    Cache-inhibited, guarded
 424 * 0xf000_0000  256M    FLASH
 425 */
 426#define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE2         |\
 427                                 BATL_PP_RW                     |\
 428                                 BATL_CACHEINHIBIT              |\
 429                                 BATL_GUARDEDSTORAGE)
 430#define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE          |\
 431                                 BATU_BL_256M                   |\
 432                                 BATU_VS                        |\
 433                                 BATU_VP)
 434#define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE          |\
 435                                 BATL_PP_RW                     |\
 436                                 BATL_MEMCOHERENCE)
 437#define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 438
 439/* Map the last 1M of flash where we're running from reset */
 440#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
 441                                 BATL_PP_RW                     |\
 442                                 BATL_CACHEINHIBIT              |\
 443                                 BATL_GUARDEDSTORAGE)
 444#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE                   |\
 445                                 BATU_BL_1M                     |\
 446                                 BATU_VS                        |\
 447                                 BATU_VP)
 448#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY  |\
 449                                 BATL_PP_RW                     |\
 450                                 BATL_MEMCOHERENCE)
 451#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 452
 453/*
 454 * BAT7         64M     Cache-inhibited, guarded
 455 * 0xe800_0000  64K     NAND FLASH
 456 * 0xe804_0000  128K    DUART Registers
 457 */
 458#define CONFIG_SYS_DBAT7L       (CONFIG_SYS_NAND_BASE           |\
 459                                 BATL_PP_RW                     |\
 460                                 BATL_CACHEINHIBIT              |\
 461                                 BATL_GUARDEDSTORAGE)
 462#define CONFIG_SYS_DBAT7U       (CONFIG_SYS_NAND_BASE           |\
 463                                 BATU_BL_512K                   |\
 464                                 BATU_VS                        |\
 465                                 BATU_VP)
 466#define CONFIG_SYS_IBAT7L       (CONFIG_SYS_NAND_BASE           |\
 467                                 BATL_PP_RW                     |\
 468                                 BATL_CACHEINHIBIT)
 469#define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 470
 471/*
 472 * Miscellaneous configurable options
 473 */
 474#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 475#define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 476#define CONFIG_PREBOOT                          /* enable preboot variable */
 477#define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 478
 479/*
 480 * For booting Linux, the board info and command line data
 481 * have to be in the first 16 MB of memory, since this is
 482 * the maximum mapped by the Linux kernel during initialization.
 483 */
 484#define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 485#define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 486
 487/*
 488 * Environment Configuration
 489 */
 490#define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 491#define CONFIG_ENV_SIZE         0x8000
 492#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 493
 494/*
 495 * Flash memory map:
 496 * fffc0000 - ffffffff  Pri FDT (256KB)
 497 * fff80000 - fffbffff  Pri U-Boot Environment (256 KB)
 498 * fff00000 - fff7ffff  Pri U-Boot (512 KB)
 499 * fef00000 - ffefffff  Pri OS image (16MB)
 500 * f8000000 - feefffff  Pri OS Use/Filesystem (111MB)
 501 *
 502 * f7fc0000 - f7ffffff  Sec FDT (256KB)
 503 * f7f80000 - f7fbffff  Sec U-Boot Environment (256 KB)
 504 * f7f00000 - f7f7ffff  Sec U-Boot (512 KB)
 505 * f6f00000 - f7efffff  Sec OS image (16MB)
 506 * f0000000 - f6efffff  Sec OS Use/Filesystem (111MB)
 507 */
 508#define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff00000)
 509#define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f00000)
 510#define CONFIG_FDT1_ENV_ADDR    __stringify(0xfffc0000)
 511#define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7fc0000)
 512#define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 513#define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 514
 515#define CONFIG_PROG_UBOOT1                                              \
 516        "$download_cmd $loadaddr $ubootfile; "                          \
 517        "if test $? -eq 0; then "                                       \
 518                "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 519                "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 520                "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 521                "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 522                "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 523                "if test $? -ne 0; then "                               \
 524                        "echo PROGRAM FAILED; "                         \
 525                "else; "                                                \
 526                        "echo PROGRAM SUCCEEDED; "                      \
 527                "fi; "                                                  \
 528        "else; "                                                        \
 529                "echo DOWNLOAD FAILED; "                                \
 530        "fi;"
 531
 532#define CONFIG_PROG_UBOOT2                                              \
 533        "$download_cmd $loadaddr $ubootfile; "                          \
 534        "if test $? -eq 0; then "                                       \
 535                "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 536                "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 537                "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 538                "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 539                "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 540                "if test $? -ne 0; then "                               \
 541                        "echo PROGRAM FAILED; "                         \
 542                "else; "                                                \
 543                        "echo PROGRAM SUCCEEDED; "                      \
 544                "fi; "                                                  \
 545        "else; "                                                        \
 546                "echo DOWNLOAD FAILED; "                                \
 547        "fi;"
 548
 549#define CONFIG_BOOT_OS_NET                                              \
 550        "$download_cmd $osaddr $osfile; "                               \
 551        "if test $? -eq 0; then "                                       \
 552                "if test -n $fdtaddr; then "                            \
 553                        "$download_cmd $fdtaddr $fdtfile; "             \
 554                        "if test $? -eq 0; then "                       \
 555                                "bootm $osaddr - $fdtaddr; "            \
 556                        "else; "                                        \
 557                                "echo FDT DOWNLOAD FAILED; "            \
 558                        "fi; "                                          \
 559                "else; "                                                \
 560                        "bootm $osaddr; "                               \
 561                "fi; "                                                  \
 562        "else; "                                                        \
 563                "echo OS DOWNLOAD FAILED; "                             \
 564        "fi;"
 565
 566#define CONFIG_PROG_OS1                                                 \
 567        "$download_cmd $osaddr $osfile; "                               \
 568        "if test $? -eq 0; then "                                       \
 569                "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 570                "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 571                "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 572                "if test $? -ne 0; then "                               \
 573                        "echo OS PROGRAM FAILED; "                      \
 574                "else; "                                                \
 575                        "echo OS PROGRAM SUCCEEDED; "                   \
 576                "fi; "                                                  \
 577        "else; "                                                        \
 578                "echo OS DOWNLOAD FAILED; "                             \
 579        "fi;"
 580
 581#define CONFIG_PROG_OS2                                                 \
 582        "$download_cmd $osaddr $osfile; "                               \
 583        "if test $? -eq 0; then "                                       \
 584                "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 585                "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 586                "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 587                "if test $? -ne 0; then "                               \
 588                        "echo OS PROGRAM FAILED; "                      \
 589                "else; "                                                \
 590                        "echo OS PROGRAM SUCCEEDED; "                   \
 591                "fi; "                                                  \
 592        "else; "                                                        \
 593                "echo OS DOWNLOAD FAILED; "                             \
 594        "fi;"
 595
 596#define CONFIG_PROG_FDT1                                                \
 597        "$download_cmd $fdtaddr $fdtfile; "                             \
 598        "if test $? -eq 0; then "                                       \
 599                "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 600                "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 601                "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 602                "if test $? -ne 0; then "                               \
 603                        "echo FDT PROGRAM FAILED; "                     \
 604                "else; "                                                \
 605                        "echo FDT PROGRAM SUCCEEDED; "                  \
 606                "fi; "                                                  \
 607        "else; "                                                        \
 608                "echo FDT DOWNLOAD FAILED; "                            \
 609        "fi;"
 610
 611#define CONFIG_PROG_FDT2                                                \
 612        "$download_cmd $fdtaddr $fdtfile; "                             \
 613        "if test $? -eq 0; then "                                       \
 614                "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 615                "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 616                "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 617                "if test $? -ne 0; then "                               \
 618                        "echo FDT PROGRAM FAILED; "                     \
 619                "else; "                                                \
 620                        "echo FDT PROGRAM SUCCEEDED; "                  \
 621                "fi; "                                                  \
 622        "else; "                                                        \
 623                "echo FDT DOWNLOAD FAILED; "                            \
 624        "fi;"
 625
 626#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 627        "autoload=yes\0"                                                \
 628        "download_cmd=tftp\0"                                           \
 629        "console_args=console=ttyS0,115200\0"                           \
 630        "root_args=root=/dev/nfs rw\0"                                  \
 631        "misc_args=ip=on\0"                                             \
 632        "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 633        "bootfile=/home/user/file\0"                                    \
 634        "osfile=/home/user/board.uImage\0"                              \
 635        "fdtfile=/home/user/board.dtb\0"                                \
 636        "ubootfile=/home/user/u-boot.bin\0"                             \
 637        "fdtaddr=0x1e00000\0"                                           \
 638        "osaddr=0x1000000\0"                                            \
 639        "loadaddr=0x1000000\0"                                          \
 640        "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 641        "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 642        "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 643        "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 644        "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 645        "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 646        "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 647        "bootcmd_flash1=run set_bootargs; "                             \
 648                "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 649        "bootcmd_flash2=run set_bootargs; "                             \
 650                "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 651        "bootcmd=run bootcmd_flash1\0"
 652#endif  /* __CONFIG_H */
 653
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