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13#ifndef __LINUX_MTD_RAWNAND_H
14#define __LINUX_MTD_RAWNAND_H
15
16#include <config.h>
17
18#include <linux/compat.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/flashchip.h>
21#include <linux/mtd/bbm.h>
22#include <asm/cache.h>
23
24struct mtd_info;
25struct nand_chip;
26struct nand_flash_dev;
27struct device_node;
28
29
30struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
31 struct nand_chip *chip,
32 int *maf_id, int *dev_id,
33 struct nand_flash_dev *type);
34
35
36int nand_scan(struct mtd_info *mtd, int max_chips);
37
38
39
40
41int nand_scan_ident(struct mtd_info *mtd, int max_chips,
42 struct nand_flash_dev *table);
43int nand_scan_tail(struct mtd_info *mtd);
44
45
46void nand_release(struct mtd_info *mtd);
47
48
49void nand_wait_ready(struct mtd_info *mtd);
50
51
52
53
54
55
56#define NAND_MAX_OOBSIZE 1664
57#define NAND_MAX_PAGESIZE 16384
58
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64
65
66#define NAND_NCE 0x01
67
68#define NAND_CLE 0x02
69
70#define NAND_ALE 0x04
71
72#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
73#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
74#define NAND_CTRL_CHANGE 0x80
75
76
77
78
79#define NAND_CMD_READ0 0
80#define NAND_CMD_READ1 1
81#define NAND_CMD_RNDOUT 5
82#define NAND_CMD_PAGEPROG 0x10
83#define NAND_CMD_READOOB 0x50
84#define NAND_CMD_ERASE1 0x60
85#define NAND_CMD_STATUS 0x70
86#define NAND_CMD_SEQIN 0x80
87#define NAND_CMD_RNDIN 0x85
88#define NAND_CMD_READID 0x90
89#define NAND_CMD_ERASE2 0xd0
90#define NAND_CMD_PARAM 0xec
91#define NAND_CMD_GET_FEATURES 0xee
92#define NAND_CMD_SET_FEATURES 0xef
93#define NAND_CMD_RESET 0xff
94
95#define NAND_CMD_LOCK 0x2a
96#define NAND_CMD_UNLOCK1 0x23
97#define NAND_CMD_UNLOCK2 0x24
98
99
100#define NAND_CMD_READSTART 0x30
101#define NAND_CMD_RNDOUTSTART 0xE0
102#define NAND_CMD_CACHEDPROG 0x15
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109
110
111#define NAND_CMD_DEPLETE1 0x100
112#define NAND_CMD_DEPLETE2 0x38
113#define NAND_CMD_STATUS_MULTI 0x71
114#define NAND_CMD_STATUS_ERROR 0x72
115
116#define NAND_CMD_STATUS_ERROR0 0x73
117#define NAND_CMD_STATUS_ERROR1 0x74
118#define NAND_CMD_STATUS_ERROR2 0x75
119#define NAND_CMD_STATUS_ERROR3 0x76
120#define NAND_CMD_STATUS_RESET 0x7f
121#define NAND_CMD_STATUS_CLEAR 0xff
122
123#define NAND_CMD_NONE -1
124
125
126#define NAND_STATUS_FAIL 0x01
127#define NAND_STATUS_FAIL_N1 0x02
128#define NAND_STATUS_TRUE_READY 0x20
129#define NAND_STATUS_READY 0x40
130#define NAND_STATUS_WP 0x80
131
132#define NAND_DATA_IFACE_CHECK_ONLY -1
133
134
135
136
137typedef enum {
138 NAND_ECC_NONE,
139 NAND_ECC_SOFT,
140 NAND_ECC_HW,
141 NAND_ECC_HW_SYNDROME,
142 NAND_ECC_HW_OOB_FIRST,
143 NAND_ECC_SOFT_BCH,
144} nand_ecc_modes_t;
145
146enum nand_ecc_algo {
147 NAND_ECC_UNKNOWN,
148 NAND_ECC_HAMMING,
149 NAND_ECC_BCH,
150};
151
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154
155
156#define NAND_ECC_READ 0
157
158#define NAND_ECC_WRITE 1
159
160#define NAND_ECC_READSYN 2
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166
167
168#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
169#define NAND_ECC_MAXIMIZE BIT(1)
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174
175#define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
176
177
178#define NAND_GET_DEVICE 0x80
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184
185
186#define NAND_BUSWIDTH_16 0x00000002
187
188#define NAND_NO_PADDING 0x00000004
189
190#define NAND_CACHEPRG 0x00000008
191
192#define NAND_COPYBACK 0x00000010
193
194
195
196
197
198#define NAND_NEED_READRDY 0x00000100
199
200
201#define NAND_NO_SUBPAGE_WRITE 0x00000200
202
203
204#define NAND_BROKEN_XD 0x00000400
205
206
207#define NAND_ROM 0x00000800
208
209
210#define NAND_SUBPAGE_READ 0x00001000
211
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214
215
216#define NAND_NEED_SCRAMBLING 0x00002000
217
218
219#define NAND_ROW_ADDR_3 0x00004000
220
221
222#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
223
224
225#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
226#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
227#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
228
229
230
231#define NAND_SKIP_BBTSCAN 0x00010000
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234
235
236#define NAND_OWN_BUFFERS 0x00020000
237
238#define NAND_SCAN_SILENT_NODEV 0x00040000
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244
245#define NAND_BUSWIDTH_AUTO 0x00080000
246
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248
249
250#define NAND_USE_BOUNCE_BUFFER 0x00100000
251
252
253
254#define NAND_BBT_SCANNED 0x40000000
255
256#define NAND_CONTROLLER_ALLOC 0x80000000
257
258
259#define NAND_CI_CHIPNR_MSK 0x03
260#define NAND_CI_CELLTYPE_MSK 0x0C
261#define NAND_CI_CELLTYPE_SHIFT 2
262
263
264#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
265#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
266
267
268#define ONFI_TIMING_MODE_0 (1 << 0)
269#define ONFI_TIMING_MODE_1 (1 << 1)
270#define ONFI_TIMING_MODE_2 (1 << 2)
271#define ONFI_TIMING_MODE_3 (1 << 3)
272#define ONFI_TIMING_MODE_4 (1 << 4)
273#define ONFI_TIMING_MODE_5 (1 << 5)
274#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
275
276
277#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
278
279
280#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
281
282
283#define ONFI_SUBFEATURE_PARAM_LEN 4
284
285
286#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
287
288struct nand_onfi_params {
289
290
291 u8 sig[4];
292 __le16 revision;
293 __le16 features;
294 __le16 opt_cmd;
295 u8 reserved0[2];
296 __le16 ext_param_page_length;
297 u8 num_of_param_pages;
298 u8 reserved1[17];
299
300
301 char manufacturer[12];
302 char model[20];
303 u8 jedec_id;
304 __le16 date_code;
305 u8 reserved2[13];
306
307
308 __le32 byte_per_page;
309 __le16 spare_bytes_per_page;
310 __le32 data_bytes_per_ppage;
311 __le16 spare_bytes_per_ppage;
312 __le32 pages_per_block;
313 __le32 blocks_per_lun;
314 u8 lun_count;
315 u8 addr_cycles;
316 u8 bits_per_cell;
317 __le16 bb_per_lun;
318 __le16 block_endurance;
319 u8 guaranteed_good_blocks;
320 __le16 guaranteed_block_endurance;
321 u8 programs_per_page;
322 u8 ppage_attr;
323 u8 ecc_bits;
324 u8 interleaved_bits;
325 u8 interleaved_ops;
326 u8 reserved3[13];
327
328
329 u8 io_pin_capacitance_max;
330 __le16 async_timing_mode;
331 __le16 program_cache_timing_mode;
332 __le16 t_prog;
333 __le16 t_bers;
334 __le16 t_r;
335 __le16 t_ccs;
336 __le16 src_sync_timing_mode;
337 u8 src_ssync_features;
338 __le16 clk_pin_capacitance_typ;
339 __le16 io_pin_capacitance_typ;
340 __le16 input_pin_capacitance_typ;
341 u8 input_pin_capacitance_max;
342 u8 driver_strength_support;
343 __le16 t_int_r;
344 __le16 t_adl;
345 u8 reserved4[8];
346
347
348 __le16 vendor_revision;
349 u8 vendor[88];
350
351 __le16 crc;
352} __packed;
353
354#define ONFI_CRC_BASE 0x4F4E
355
356
357struct onfi_ext_ecc_info {
358 u8 ecc_bits;
359 u8 codeword_size;
360 __le16 bb_per_lun;
361 __le16 block_endurance;
362 u8 reserved[2];
363} __packed;
364
365#define ONFI_SECTION_TYPE_0 0
366#define ONFI_SECTION_TYPE_1 1
367#define ONFI_SECTION_TYPE_2 2
368struct onfi_ext_section {
369 u8 type;
370 u8 length;
371} __packed;
372
373#define ONFI_EXT_SECTION_MAX 8
374
375
376struct onfi_ext_param_page {
377 __le16 crc;
378 u8 sig[4];
379 u8 reserved0[10];
380 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
381
382
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386
387
388} __packed;
389
390struct nand_onfi_vendor_micron {
391 u8 two_plane_read;
392 u8 read_cache;
393 u8 read_unique_id;
394 u8 dq_imped;
395 u8 dq_imped_num_settings;
396 u8 dq_imped_feat_addr;
397 u8 rb_pulldown_strength;
398 u8 rb_pulldown_strength_feat_addr;
399 u8 rb_pulldown_strength_num_settings;
400 u8 otp_mode;
401 u8 otp_page_start;
402 u8 otp_data_prot_addr;
403 u8 otp_num_pages;
404 u8 otp_feat_addr;
405 u8 read_retry_options;
406 u8 reserved[72];
407 u8 param_revision;
408} __packed;
409
410struct jedec_ecc_info {
411 u8 ecc_bits;
412 u8 codeword_size;
413 __le16 bb_per_lun;
414 __le16 block_endurance;
415 u8 reserved[2];
416} __packed;
417
418
419#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
420
421struct nand_jedec_params {
422
423
424 u8 sig[4];
425 __le16 revision;
426 __le16 features;
427 u8 opt_cmd[3];
428 __le16 sec_cmd;
429 u8 num_of_param_pages;
430 u8 reserved0[18];
431
432
433 char manufacturer[12];
434 char model[20];
435 u8 jedec_id[6];
436 u8 reserved1[10];
437
438
439 __le32 byte_per_page;
440 __le16 spare_bytes_per_page;
441 u8 reserved2[6];
442 __le32 pages_per_block;
443 __le32 blocks_per_lun;
444 u8 lun_count;
445 u8 addr_cycles;
446 u8 bits_per_cell;
447 u8 programs_per_page;
448 u8 multi_plane_addr;
449 u8 multi_plane_op_attr;
450 u8 reserved3[38];
451
452
453 __le16 async_sdr_speed_grade;
454 __le16 toggle_ddr_speed_grade;
455 __le16 sync_ddr_speed_grade;
456 u8 async_sdr_features;
457 u8 toggle_ddr_features;
458 u8 sync_ddr_features;
459 __le16 t_prog;
460 __le16 t_bers;
461 __le16 t_r;
462 __le16 t_r_multi_plane;
463 __le16 t_ccs;
464 __le16 io_pin_capacitance_typ;
465 __le16 input_pin_capacitance_typ;
466 __le16 clk_pin_capacitance_typ;
467 u8 driver_strength_support;
468 __le16 t_adl;
469 u8 reserved4[36];
470
471
472 u8 guaranteed_good_blocks;
473 __le16 guaranteed_block_endurance;
474 struct jedec_ecc_info ecc_info[4];
475 u8 reserved5[29];
476
477
478 u8 reserved6[148];
479
480
481 __le16 vendor_rev_num;
482 u8 reserved7[88];
483
484
485 __le16 crc;
486} __packed;
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495
496struct nand_hw_control {
497 spinlock_t lock;
498 struct nand_chip *active;
499};
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507struct nand_ecc_step_info {
508 int stepsize;
509 const int *strengths;
510 int nstrengths;
511};
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518
519struct nand_ecc_caps {
520 const struct nand_ecc_step_info *stepinfos;
521 int nstepinfos;
522 int (*calc_ecc_bytes)(int step_size, int strength);
523};
524
525
526#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
527static const int __name##_strengths[] = { __VA_ARGS__ }; \
528static const struct nand_ecc_step_info __name##_stepinfo = { \
529 .stepsize = __step, \
530 .strengths = __name##_strengths, \
531 .nstrengths = ARRAY_SIZE(__name##_strengths), \
532}; \
533static const struct nand_ecc_caps __name = { \
534 .stepinfos = &__name##_stepinfo, \
535 .nstepinfos = 1, \
536 .calc_ecc_bytes = __calc, \
537}
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591struct nand_ecc_ctrl {
592 nand_ecc_modes_t mode;
593 enum nand_ecc_algo algo;
594 int steps;
595 int size;
596 int bytes;
597 int total;
598 int strength;
599 int prepad;
600 int postpad;
601 unsigned int options;
602 struct nand_ecclayout *layout;
603 void *priv;
604 void (*hwctl)(struct mtd_info *mtd, int mode);
605 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
606 uint8_t *ecc_code);
607 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
608 uint8_t *calc_ecc);
609 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
610 uint8_t *buf, int oob_required, int page);
611 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
612 const uint8_t *buf, int oob_required, int page);
613 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
614 uint8_t *buf, int oob_required, int page);
615 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
616 uint32_t offs, uint32_t len, uint8_t *buf, int page);
617 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
618 uint32_t offset, uint32_t data_len,
619 const uint8_t *data_buf, int oob_required, int page);
620 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
621 const uint8_t *buf, int oob_required, int page);
622 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
623 int page);
624 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
625 int page);
626 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
627 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
628 int page);
629};
630
631static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
632{
633 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
634}
635
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643
644
645struct nand_buffers {
646 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
647 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
648 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
649 ARCH_DMA_MINALIGN)];
650};
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703struct nand_sdr_timings {
704 u64 tBERS_max;
705 u32 tCCS_min;
706 u64 tPROG_max;
707 u64 tR_max;
708 u32 tALH_min;
709 u32 tADL_min;
710 u32 tALS_min;
711 u32 tAR_min;
712 u32 tCEA_max;
713 u32 tCEH_min;
714 u32 tCH_min;
715 u32 tCHZ_max;
716 u32 tCLH_min;
717 u32 tCLR_min;
718 u32 tCLS_min;
719 u32 tCOH_min;
720 u32 tCS_min;
721 u32 tDH_min;
722 u32 tDS_min;
723 u32 tFEAT_max;
724 u32 tIR_min;
725 u32 tITC_max;
726 u32 tRC_min;
727 u32 tREA_max;
728 u32 tREH_min;
729 u32 tRHOH_min;
730 u32 tRHW_min;
731 u32 tRHZ_max;
732 u32 tRLOH_min;
733 u32 tRP_min;
734 u32 tRR_min;
735 u64 tRST_max;
736 u32 tWB_max;
737 u32 tWC_min;
738 u32 tWH_min;
739 u32 tWHR_min;
740 u32 tWP_min;
741 u32 tWW_min;
742};
743
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746
747
748enum nand_data_interface_type {
749 NAND_SDR_IFACE,
750};
751
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756
757struct nand_data_interface {
758 enum nand_data_interface_type type;
759 union {
760 struct nand_sdr_timings sdr;
761 } timings;
762};
763
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767
768static inline const struct nand_sdr_timings *
769nand_get_sdr_timings(const struct nand_data_interface *conf)
770{
771 if (conf->type != NAND_SDR_IFACE)
772 return ERR_PTR(-EINVAL);
773
774 return &conf->timings.sdr;
775}
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880struct nand_chip {
881 struct mtd_info mtd;
882 void __iomem *IO_ADDR_R;
883 void __iomem *IO_ADDR_W;
884
885 int flash_node;
886
887 uint8_t (*read_byte)(struct mtd_info *mtd);
888 u16 (*read_word)(struct mtd_info *mtd);
889 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
890 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
891 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
892 void (*select_chip)(struct mtd_info *mtd, int chip);
893 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
894 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
895 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
896 int (*dev_ready)(struct mtd_info *mtd);
897 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
898 int page_addr);
899 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
900 int (*erase)(struct mtd_info *mtd, int page);
901 int (*scan_bbt)(struct mtd_info *mtd);
902 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
903 uint32_t offset, int data_len, const uint8_t *buf,
904 int oob_required, int page, int raw);
905 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
906 int feature_addr, uint8_t *subfeature_para);
907 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
908 int feature_addr, uint8_t *subfeature_para);
909 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
910 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
911 const struct nand_data_interface *conf);
912
913
914 int chip_delay;
915 unsigned int options;
916 unsigned int bbt_options;
917
918 int page_shift;
919 int phys_erase_shift;
920 int bbt_erase_shift;
921 int chip_shift;
922 int numchips;
923 uint64_t chipsize;
924 int pagemask;
925 int pagebuf;
926 unsigned int pagebuf_bitflips;
927 int subpagesize;
928 uint8_t bits_per_cell;
929 uint16_t ecc_strength_ds;
930 uint16_t ecc_step_ds;
931 int onfi_timing_mode_default;
932 int badblockpos;
933 int badblockbits;
934
935 int onfi_version;
936 int jedec_version;
937 struct nand_onfi_params onfi_params;
938 struct nand_jedec_params jedec_params;
939
940 struct nand_data_interface *data_interface;
941
942 int read_retries;
943
944 flstate_t state;
945
946 uint8_t *oob_poi;
947 struct nand_hw_control *controller;
948 struct nand_ecclayout *ecclayout;
949
950 struct nand_ecc_ctrl ecc;
951 struct nand_buffers *buffers;
952 unsigned long buf_align;
953 struct nand_hw_control hwcontrol;
954
955 uint8_t *bbt;
956 struct nand_bbt_descr *bbt_td;
957 struct nand_bbt_descr *bbt_md;
958
959 struct nand_bbt_descr *badblock_pattern;
960
961 void *priv;
962};
963
964static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
965{
966 return container_of(mtd, struct nand_chip, mtd);
967}
968
969static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
970{
971 return &chip->mtd;
972}
973
974static inline void *nand_get_controller_data(struct nand_chip *chip)
975{
976 return chip->priv;
977}
978
979static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
980{
981 chip->priv = priv;
982}
983
984
985
986
987#define NAND_MFR_TOSHIBA 0x98
988#define NAND_MFR_SAMSUNG 0xec
989#define NAND_MFR_FUJITSU 0x04
990#define NAND_MFR_NATIONAL 0x8f
991#define NAND_MFR_RENESAS 0x07
992#define NAND_MFR_STMICRO 0x20
993#define NAND_MFR_HYNIX 0xad
994#define NAND_MFR_MICRON 0x2c
995#define NAND_MFR_AMD 0x01
996#define NAND_MFR_MACRONIX 0xc2
997#define NAND_MFR_EON 0x92
998#define NAND_MFR_SANDISK 0x45
999#define NAND_MFR_INTEL 0x89
1000#define NAND_MFR_ATO 0x9b
1001
1002
1003#define NAND_MAX_ID_LEN 8
1004
1005
1006
1007
1008
1009
1010#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1011 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1012 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1025 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1026 .options = (opts) }
1027
1028#define NAND_ECC_INFO(_strength, _step) \
1029 { .strength_ds = (_strength), .step_ds = (_step) }
1030#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1031#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062struct nand_flash_dev {
1063 char *name;
1064 union {
1065 struct {
1066 uint8_t mfr_id;
1067 uint8_t dev_id;
1068 };
1069 uint8_t id[NAND_MAX_ID_LEN];
1070 };
1071 unsigned int pagesize;
1072 unsigned int chipsize;
1073 unsigned int erasesize;
1074 unsigned int options;
1075 uint16_t id_len;
1076 uint16_t oobsize;
1077 struct {
1078 uint16_t strength_ds;
1079 uint16_t step_ds;
1080 } ecc;
1081 int onfi_timing_mode_default;
1082};
1083
1084
1085
1086
1087
1088
1089struct nand_manufacturers {
1090 int id;
1091 char *name;
1092};
1093
1094extern struct nand_flash_dev nand_flash_ids[];
1095extern struct nand_manufacturers nand_manuf_ids[];
1096
1097int nand_default_bbt(struct mtd_info *mtd);
1098int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1099int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1100int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1101int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1102 int allowbbt);
1103int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1104 size_t *retlen, uint8_t *buf);
1105
1106
1107
1108
1109#define NAND_SMALL_BADBLOCK_POS 5
1110#define NAND_LARGE_BADBLOCK_POS 0
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123struct platform_nand_chip {
1124 int nr_chips;
1125 int chip_offset;
1126 int nr_partitions;
1127 struct mtd_partition *partitions;
1128 int chip_delay;
1129 unsigned int options;
1130 unsigned int bbt_options;
1131 const char **part_probe_types;
1132};
1133
1134
1135struct platform_device;
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153struct platform_nand_ctrl {
1154 int (*probe)(struct platform_device *pdev);
1155 void (*remove)(struct platform_device *pdev);
1156 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1157 int (*dev_ready)(struct mtd_info *mtd);
1158 void (*select_chip)(struct mtd_info *mtd, int chip);
1159 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1160 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1161 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1162 unsigned char (*read_byte)(struct mtd_info *mtd);
1163 void *priv;
1164};
1165
1166
1167
1168
1169
1170
1171struct platform_nand_data {
1172 struct platform_nand_chip chip;
1173 struct platform_nand_ctrl ctrl;
1174};
1175
1176#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1177
1178static inline int onfi_feature(struct nand_chip *chip)
1179{
1180 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1181}
1182
1183
1184static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1185{
1186 if (!chip->onfi_version)
1187 return ONFI_TIMING_MODE_UNKNOWN;
1188 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1189}
1190
1191
1192static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1193{
1194 if (!chip->onfi_version)
1195 return ONFI_TIMING_MODE_UNKNOWN;
1196 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1197}
1198#else
1199static inline int onfi_feature(struct nand_chip *chip)
1200{
1201 return 0;
1202}
1203
1204static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1205{
1206 return ONFI_TIMING_MODE_UNKNOWN;
1207}
1208
1209static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1210{
1211 return ONFI_TIMING_MODE_UNKNOWN;
1212}
1213#endif
1214
1215int onfi_init_data_interface(struct nand_chip *chip,
1216 struct nand_data_interface *iface,
1217 enum nand_data_interface_type type,
1218 int timing_mode);
1219
1220
1221
1222
1223
1224
1225static inline bool nand_is_slc(struct nand_chip *chip)
1226{
1227 return chip->bits_per_cell == 1;
1228}
1229
1230
1231
1232
1233
1234static inline int nand_opcode_8bits(unsigned int command)
1235{
1236 switch (command) {
1237 case NAND_CMD_READID:
1238 case NAND_CMD_PARAM:
1239 case NAND_CMD_GET_FEATURES:
1240 case NAND_CMD_SET_FEATURES:
1241 return 1;
1242 default:
1243 break;
1244 }
1245 return 0;
1246}
1247
1248
1249static inline int jedec_feature(struct nand_chip *chip)
1250{
1251 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1252 : 0;
1253}
1254
1255
1256void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1257void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1258void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1259void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1260uint8_t nand_read_byte(struct mtd_info *mtd);
1261
1262
1263const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1264
1265const struct nand_data_interface *nand_get_default_data_interface(void);
1266
1267int nand_check_erased_ecc_chunk(void *data, int datalen,
1268 void *ecc, int ecclen,
1269 void *extraoob, int extraooblen,
1270 int threshold);
1271
1272int nand_check_ecc_caps(struct nand_chip *chip,
1273 const struct nand_ecc_caps *caps, int oobavail);
1274
1275int nand_match_ecc_req(struct nand_chip *chip,
1276 const struct nand_ecc_caps *caps, int oobavail);
1277
1278int nand_maximize_ecc(struct nand_chip *chip,
1279 const struct nand_ecc_caps *caps, int oobavail);
1280
1281
1282int nand_reset(struct nand_chip *chip, int chipnr);
1283#endif
1284