LXR uboot/include/phy.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2011 Freescale Semiconductor, Inc.
   4 *      Andy Fleming <afleming@gmail.com>
   5 *
   6 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
   7 */
   8
   9#ifndef _PHY_H
  10#define _PHY_H
  11
  12#include <dm.h>
  13#include <linux/list.h>
  14#include <linux/mii.h>
  15#include <linux/ethtool.h>
  16#include <linux/mdio.h>
  17#include <phy_interface.h>
  18
  19#define PHY_FIXED_ID            0xa5a55a5a
  20
  21#define PHY_MAX_ADDR 32
  22
  23#define PHY_FLAG_BROKEN_RESET   (1 << 0) /* soft reset not supported */
  24
  25#define PHY_DEFAULT_FEATURES    (SUPPORTED_Autoneg | \
  26                                 SUPPORTED_TP | \
  27                                 SUPPORTED_MII)
  28
  29#define PHY_10BT_FEATURES       (SUPPORTED_10baseT_Half | \
  30                                 SUPPORTED_10baseT_Full)
  31
  32#define PHY_100BT_FEATURES      (SUPPORTED_100baseT_Half | \
  33                                 SUPPORTED_100baseT_Full)
  34
  35#define PHY_1000BT_FEATURES     (SUPPORTED_1000baseT_Half | \
  36                                 SUPPORTED_1000baseT_Full)
  37
  38#define PHY_BASIC_FEATURES      (PHY_10BT_FEATURES | \
  39                                 PHY_100BT_FEATURES | \
  40                                 PHY_DEFAULT_FEATURES)
  41
  42#define PHY_GBIT_FEATURES       (PHY_BASIC_FEATURES | \
  43                                 PHY_1000BT_FEATURES)
  44
  45#define PHY_10G_FEATURES        (PHY_GBIT_FEATURES | \
  46                                SUPPORTED_10000baseT_Full)
  47
  48#ifndef PHY_ANEG_TIMEOUT
  49#define PHY_ANEG_TIMEOUT        4000
  50#endif
  51
  52
  53struct phy_device;
  54
  55#define MDIO_NAME_LEN 32
  56
  57struct mii_dev {
  58        struct list_head link;
  59        char name[MDIO_NAME_LEN];
  60        void *priv;
  61        int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
  62        int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
  63                        u16 val);
  64        int (*reset)(struct mii_dev *bus);
  65        struct phy_device *phymap[PHY_MAX_ADDR];
  66        u32 phy_mask;
  67};
  68
  69/* struct phy_driver: a structure which defines PHY behavior
  70 *
  71 * uid will contain a number which represents the PHY.  During
  72 * startup, the driver will poll the PHY to find out what its
  73 * UID--as defined by registers 2 and 3--is.  The 32-bit result
  74 * gotten from the PHY will be masked to
  75 * discard any bits which may change based on revision numbers
  76 * unimportant to functionality
  77 *
  78 */
  79struct phy_driver {
  80        char *name;
  81        unsigned int uid;
  82        unsigned int mask;
  83        unsigned int mmds;
  84
  85        u32 features;
  86
  87        /* Called to do any driver startup necessities */
  88        /* Will be called during phy_connect */
  89        int (*probe)(struct phy_device *phydev);
  90
  91        /* Called to configure the PHY, and modify the controller
  92         * based on the results.  Should be called after phy_connect */
  93        int (*config)(struct phy_device *phydev);
  94
  95        /* Called when starting up the controller */
  96        int (*startup)(struct phy_device *phydev);
  97
  98        /* Called when bringing down the controller */
  99        int (*shutdown)(struct phy_device *phydev);
 100
 101        int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
 102        int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
 103                        u16 val);
 104        struct list_head list;
 105};
 106
 107struct phy_device {
 108        /* Information about the PHY type */
 109        /* And management functions */
 110        struct mii_dev *bus;
 111        struct phy_driver *drv;
 112        void *priv;
 113
 114#ifdef CONFIG_DM_ETH
 115        struct udevice *dev;
 116        ofnode node;
 117#else
 118        struct eth_device *dev;
 119#endif
 120
 121        /* forced speed & duplex (no autoneg)
 122         * partner speed & duplex & pause (autoneg)
 123         */
 124        int speed;
 125        int duplex;
 126
 127        /* The most recently read link state */
 128        int link;
 129        int port;
 130        phy_interface_t interface;
 131
 132        u32 advertising;
 133        u32 supported;
 134        u32 mmds;
 135
 136        int autoneg;
 137        int addr;
 138        int pause;
 139        int asym_pause;
 140        u32 phy_id;
 141        bool is_c45;
 142        u32 flags;
 143};
 144
 145struct fixed_link {
 146        int phy_id;
 147        int duplex;
 148        int link_speed;
 149        int pause;
 150        int asym_pause;
 151};
 152
 153static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
 154{
 155        struct mii_dev *bus = phydev->bus;
 156
 157        return bus->read(bus, phydev->addr, devad, regnum);
 158}
 159
 160static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
 161                        u16 val)
 162{
 163        struct mii_dev *bus = phydev->bus;
 164
 165        return bus->write(bus, phydev->addr, devad, regnum, val);
 166}
 167
 168#ifdef CONFIG_PHYLIB_10G
 169extern struct phy_driver gen10g_driver;
 170
 171/* For now, XGMII is the only 10G interface */
 172static inline int is_10g_interface(phy_interface_t interface)
 173{
 174        return interface == PHY_INTERFACE_MODE_XGMII;
 175}
 176
 177#endif
 178
 179int phy_init(void);
 180int phy_reset(struct phy_device *phydev);
 181struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
 182                phy_interface_t interface);
 183#ifdef CONFIG_DM_ETH
 184void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
 185struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 186                                struct udevice *dev,
 187                                phy_interface_t interface);
 188static inline ofnode phy_get_ofnode(struct phy_device *phydev)
 189{
 190        if (ofnode_valid(phydev->node))
 191                return phydev->node;
 192        else
 193                return dev_ofnode(phydev->dev);
 194}
 195#else
 196void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
 197struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 198                                struct eth_device *dev,
 199                                phy_interface_t interface);
 200static inline ofnode phy_get_ofnode(struct phy_device *phydev)
 201{
 202        return ofnode_null();
 203}
 204#endif
 205int phy_startup(struct phy_device *phydev);
 206int phy_config(struct phy_device *phydev);
 207int phy_shutdown(struct phy_device *phydev);
 208int phy_register(struct phy_driver *drv);
 209int phy_set_supported(struct phy_device *phydev, u32 max_speed);
 210int genphy_config_aneg(struct phy_device *phydev);
 211int genphy_restart_aneg(struct phy_device *phydev);
 212int genphy_update_link(struct phy_device *phydev);
 213int genphy_parse_link(struct phy_device *phydev);
 214int genphy_config(struct phy_device *phydev);
 215int genphy_startup(struct phy_device *phydev);
 216int genphy_shutdown(struct phy_device *phydev);
 217int gen10g_config(struct phy_device *phydev);
 218int gen10g_startup(struct phy_device *phydev);
 219int gen10g_shutdown(struct phy_device *phydev);
 220int gen10g_discover_mmds(struct phy_device *phydev);
 221
 222int phy_b53_init(void);
 223int phy_mv88e61xx_init(void);
 224int phy_aquantia_init(void);
 225int phy_atheros_init(void);
 226int phy_broadcom_init(void);
 227int phy_cortina_init(void);
 228int phy_davicom_init(void);
 229int phy_et1011c_init(void);
 230int phy_lxt_init(void);
 231int phy_marvell_init(void);
 232int phy_micrel_ksz8xxx_init(void);
 233int phy_micrel_ksz90x1_init(void);
 234int phy_meson_gxl_init(void);
 235int phy_natsemi_init(void);
 236int phy_realtek_init(void);
 237int phy_smsc_init(void);
 238int phy_teranetics_init(void);
 239int phy_ti_init(void);
 240int phy_vitesse_init(void);
 241int phy_xilinx_init(void);
 242int phy_mscc_init(void);
 243int phy_fixed_init(void);
 244
 245int board_phy_config(struct phy_device *phydev);
 246int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
 247
 248/**
 249 * phy_get_interface_by_name() - Look up a PHY interface name
 250 *
 251 * @str:        PHY interface name, e.g. "mii"
 252 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 253 */
 254int phy_get_interface_by_name(const char *str);
 255
 256/**
 257 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 258 * is RGMII (all variants)
 259 * @phydev: the phy_device struct
 260 */
 261static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 262{
 263        return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
 264                phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 265}
 266
 267/**
 268 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 269 * is SGMII (all variants)
 270 * @phydev: the phy_device struct
 271 */
 272static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
 273{
 274        return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
 275                phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
 276}
 277
 278/* PHY UIDs for various PHYs that are referenced in external code */
 279#define PHY_UID_CS4340          0x13e51002
 280#define PHY_UID_CS4223          0x03e57003
 281#define PHY_UID_TN2020          0x00a19410
 282#define PHY_UID_IN112525_S03    0x02107440
 283
 284#endif
 285