1/* 2 * hardware_ti816x.h 3 * 4 * TI816x hardware specific header 5 * 6 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 7 * Antoine Tenart, <atenart@adeneo-embedded.com> 8 * Based on TI-PSP-04.00.02.14 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21#ifndef __AM33XX_HARDWARE_TI816X_H 22#define __AM33XX_HARDWARE_TI816X_H 23 24/* UART */ 25#define UART0_BASE 0x48020000 26#define UART1_BASE 0x48022000 27#define UART2_BASE 0x48024000 28 29/* Watchdog Timer */ 30#define WDT_BASE 0x480C2000 31 32/* Control Module Base Address */ 33#define CTRL_BASE 0x48140000 34#define CTRL_DEVICE_BASE 0x48140600 35 36/* PRCM Base Address */ 37#define PRCM_BASE 0x48180000 38 39#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 40#define PRM_RSTST (PRM_RSTCTRL + 8) 41 42/* VTP Base address */ 43#define VTP0_CTRL_ADDR 0x48198358 44#define VTP1_CTRL_ADDR 0x4819A358 45 46/* DDR Base address */ 47#define DDR_PHY_CMD_ADDR 0x48198000 48#define DDR_PHY_DATA_ADDR 0x481980C8 49#define DDR_PHY_CMD_ADDR2 0x4819A000 50#define DDR_PHY_DATA_ADDR2 0x4819A0C8 51#define DDR_DATA_REGS_NR 4 52 53 54#define DDRPHY_0_CONFIG_BASE 0x48198000 55#define DDRPHY_1_CONFIG_BASE 0x4819A000 56#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ 57 DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) 58 59/* RTC base address */ 60#define RTC_BASE 0x480C0000 61 62#endif /* __AM33XX_HARDWARE_TI816X_H */ 63