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9#ifndef _ASM_ARCH_CLOCK_H
10#define _ASM_ARCH_CLOCK_H
11
12#include <common.h>
13#include <asm/arch/crm_regs.h>
14
15#ifdef CONFIG_SYS_MX7_HCLK
16#define MXC_HCLK CONFIG_SYS_MX7_HCLK
17#else
18#define MXC_HCLK 24000000
19#endif
20
21#ifdef CONFIG_SYS_MX7_CLK32
22#define MXC_CLK32 CONFIG_SYS_MX7_CLK32
23#else
24#define MXC_CLK32 32768
25#endif
26
27
28enum mxc_clock {
29 MXC_ARM_CLK = 0,
30 MXC_AHB_CLK,
31 MXC_IPG_CLK,
32 MXC_UART_CLK,
33 MXC_CSPI_CLK,
34 MXC_AXI_CLK,
35 MXC_DDR_CLK,
36 MXC_ESDHC_CLK,
37 MXC_ESDHC2_CLK,
38 MXC_ESDHC3_CLK,
39 MXC_I2C_CLK,
40};
41
42
43enum pll_clocks {
44 PLL_CORE,
45 PLL_SYS,
46 PLL_ENET,
47 PLL_AUDIO,
48 PLL_VIDEO,
49 PLL_DDR,
50 PLL_USB,
51};
52
53
54enum clk_root_src {
55 OSC_24M_CLK,
56
57 PLL_ARM_MAIN_800M_CLK,
58
59 PLL_SYS_MAIN_480M_CLK,
60 PLL_SYS_MAIN_240M_CLK,
61 PLL_SYS_MAIN_120M_CLK,
62 PLL_SYS_PFD0_392M_CLK,
63 PLL_SYS_PFD0_196M_CLK,
64 PLL_SYS_PFD1_332M_CLK,
65 PLL_SYS_PFD1_166M_CLK,
66 PLL_SYS_PFD2_270M_CLK,
67 PLL_SYS_PFD2_135M_CLK,
68 PLL_SYS_PFD3_CLK,
69 PLL_SYS_PFD4_CLK,
70 PLL_SYS_PFD5_CLK,
71 PLL_SYS_PFD6_CLK,
72 PLL_SYS_PFD7_CLK,
73
74 PLL_ENET_MAIN_500M_CLK,
75 PLL_ENET_MAIN_250M_CLK,
76 PLL_ENET_MAIN_125M_CLK,
77 PLL_ENET_MAIN_100M_CLK,
78 PLL_ENET_MAIN_50M_CLK,
79 PLL_ENET_MAIN_40M_CLK,
80 PLL_ENET_MAIN_25M_CLK,
81
82 PLL_DRAM_MAIN_1066M_CLK,
83 PLL_DRAM_MAIN_533M_CLK,
84
85 PLL_AUDIO_MAIN_CLK,
86 PLL_VIDEO_MAIN_CLK,
87
88 PLL_USB_MAIN_480M_CLK,
89
90 EXT_CLK_1,
91 EXT_CLK_2,
92 EXT_CLK_3,
93 EXT_CLK_4,
94
95 REF_1M_CLK,
96 OSC_32K_CLK,
97};
98
99
100
101
102enum clk_root_index {
103 ARM_A7_CLK_ROOT = 0,
104 ARM_M4_CLK_ROOT = 1,
105 ARM_M0_CLK_ROOT = 2,
106 MAIN_AXI_CLK_ROOT = 16,
107 DISP_AXI_CLK_ROOT = 17,
108 ENET_AXI_CLK_ROOT = 18,
109 NAND_USDHC_BUS_CLK_ROOT = 19,
110 AHB_CLK_ROOT = 32,
111 DRAM_PHYM_CLK_ROOT = 48,
112 DRAM_CLK_ROOT = 49,
113 DRAM_PHYM_ALT_CLK_ROOT = 64,
114 DRAM_ALT_CLK_ROOT = 65,
115 USB_HSIC_CLK_ROOT = 66,
116 PCIE_CTRL_CLK_ROOT = 67,
117 PCIE_PHY_CLK_ROOT = 68,
118 EPDC_PIXEL_CLK_ROOT = 69,
119 LCDIF_PIXEL_CLK_ROOT = 70,
120 MIPI_DSI_EXTSER_CLK_ROOT = 71,
121 MIPI_CSI_WARP_CLK_ROOT = 72,
122 MIPI_DPHY_REF_CLK_ROOT = 73,
123 SAI1_CLK_ROOT = 74,
124 SAI2_CLK_ROOT = 75,
125 SAI3_CLK_ROOT = 76,
126 SPDIF_CLK_ROOT = 77,
127 ENET1_REF_CLK_ROOT = 78,
128 ENET1_TIME_CLK_ROOT = 79,
129 ENET2_REF_CLK_ROOT = 80,
130 ENET2_TIME_CLK_ROOT = 81,
131 ENET_PHY_REF_CLK_ROOT = 82,
132 EIM_CLK_ROOT = 83,
133 NAND_CLK_ROOT = 84,
134 QSPI_CLK_ROOT = 85,
135 USDHC1_CLK_ROOT = 86,
136 USDHC2_CLK_ROOT = 87,
137 USDHC3_CLK_ROOT = 88,
138 CAN1_CLK_ROOT = 89,
139 CAN2_CLK_ROOT = 90,
140 I2C1_CLK_ROOT = 91,
141 I2C2_CLK_ROOT = 92,
142 I2C3_CLK_ROOT = 93,
143 I2C4_CLK_ROOT = 94,
144 UART1_CLK_ROOT = 95,
145 UART2_CLK_ROOT = 96,
146 UART3_CLK_ROOT = 97,
147 UART4_CLK_ROOT = 98,
148 UART5_CLK_ROOT = 99,
149 UART6_CLK_ROOT = 100,
150 UART7_CLK_ROOT = 101,
151 ECSPI1_CLK_ROOT = 102,
152 ECSPI2_CLK_ROOT = 103,
153 ECSPI3_CLK_ROOT = 104,
154 ECSPI4_CLK_ROOT = 105,
155 PWM1_CLK_ROOT = 106,
156 PWM2_CLK_ROOT = 107,
157 PWM3_CLK_ROOT = 108,
158 PWM4_CLK_ROOT = 109,
159 FLEXTIMER1_CLK_ROOT = 110,
160 FLEXTIMER2_CLK_ROOT = 111,
161 SIM1_CLK_ROOT = 112,
162 SIM2_CLK_ROOT = 113,
163 GPT1_CLK_ROOT = 114,
164 GPT2_CLK_ROOT = 115,
165 GPT3_CLK_ROOT = 116,
166 GPT4_CLK_ROOT = 117,
167 TRACE_CLK_ROOT = 118,
168 WDOG_CLK_ROOT = 119,
169 CSI_MCLK_CLK_ROOT = 120,
170 AUDIO_MCLK_CLK_ROOT = 121,
171 WRCLK_CLK_ROOT = 122,
172 IPP_DO_CLKO1 = 123,
173 IPP_DO_CLKO2 = 124,
174
175 CLK_ROOT_MAX,
176};
177
178#if (CONFIG_CONS_INDEX == 0)
179#define UART_CLK_ROOT UART1_CLK_ROOT
180#elif (CONFIG_CONS_INDEX == 1)
181#define UART_CLK_ROOT UART2_CLK_ROOT
182#elif (CONFIG_CONS_INDEX == 2)
183#define UART_CLK_ROOT UART3_CLK_ROOT
184#elif (CONFIG_CONS_INDEX == 3)
185#define UART_CLK_ROOT UART4_CLK_ROOT
186#elif (CONFIG_CONS_INDEX == 4)
187#define UART_CLK_ROOT UART5_CLK_ROOT
188#elif (CONFIG_CONS_INDEX == 5)
189#define UART_CLK_ROOT UART6_CLK_ROOT
190#elif (CONFIG_CONS_INDEX == 6)
191#define UART_CLK_ROOT UART7_CLK_ROOT
192#else
193#error "Invalid IMX UART ID for serial console is defined"
194#endif
195
196struct clk_root_setting {
197 enum clk_root_index root;
198 u32 setting;
199};
200
201
202
203
204enum clk_ccgr_index {
205 CCGR_CPU = 0,
206 CCGR_M4 = 1,
207 CCGR_SIM_MAIN = 4,
208 CCGR_SIM_DISPLAY = 5,
209 CCGR_SIM_ENET = 6,
210 CCGR_SIM_M = 7,
211 CCGR_SIM_S = 8,
212 CCGR_SIM_WAKEUP = 9,
213 CCGR_IPMUX1 = 10,
214 CCGR_IPMUX2 = 11,
215 CCGR_IPMUX3 = 12,
216 CCGR_ROM = 16,
217 CCGR_OCRAM = 17,
218 CCGR_OCRAM_S = 18,
219 CCGR_DRAM = 19,
220 CCGR_RAWNAND = 20,
221 CCGR_QSPI = 21,
222 CCGR_WEIM = 22,
223 CCGR_ADC = 32,
224 CCGR_ANATOP = 33,
225 CCGR_SCTR = 34,
226 CCGR_OCOTP = 35,
227 CCGR_CAAM = 36,
228 CCGR_SNVS = 37,
229 CCGR_RDC = 38,
230 CCGR_MU = 39,
231 CCGR_HS = 40,
232 CCGR_DVFS = 41,
233 CCGR_QOS = 42,
234 CCGR_QOS_DISPMIX = 43,
235 CCGR_QOS_MEGAMIX = 44,
236 CCGR_CSU = 45,
237 CCGR_DBGMON = 46,
238 CCGR_DEBUG = 47,
239 CCGR_TRACE = 48,
240 CCGR_SEC_DEBUG = 49,
241 CCGR_SEMA1 = 64,
242 CCGR_SEMA2 = 65,
243 CCGR_PERFMON1 = 68,
244 CCGR_PERFMON2 = 69,
245 CCGR_SDMA = 72,
246 CCGR_CSI = 73,
247 CCGR_EPDC = 74,
248 CCGR_LCDIF = 75,
249 CCGR_PXP = 76,
250 CCGR_PCIE = 96,
251 CCGR_MIPI_CSI = 100,
252 CCGR_MIPI_DSI = 101,
253 CCGR_MIPI_MEM_PHY = 102,
254 CCGR_USB_CTRL = 104,
255 CCGR_USB_HSIC = 105,
256 CCGR_USB_PHY1 = 106,
257 CCGR_USB_PHY2 = 107,
258 CCGR_USDHC1 = 108,
259 CCGR_USDHC2 = 109,
260 CCGR_USDHC3 = 110,
261 CCGR_ENET1 = 112,
262 CCGR_ENET2 = 113,
263 CCGR_CAN1 = 116,
264 CCGR_CAN2 = 117,
265 CCGR_ECSPI1 = 120,
266 CCGR_ECSPI2 = 121,
267 CCGR_ECSPI3 = 122,
268 CCGR_ECSPI4 = 123,
269 CCGR_GPT1 = 124,
270 CCGR_GPT2 = 125,
271 CCGR_GPT3 = 126,
272 CCGR_GPT4 = 127,
273 CCGR_FTM1 = 128,
274 CCGR_FTM2 = 129,
275 CCGR_PWM1 = 132,
276 CCGR_PWM2 = 133,
277 CCGR_PWM3 = 134,
278 CCGR_PWM4 = 135,
279 CCGR_I2C1 = 136,
280 CCGR_I2C2 = 137,
281 CCGR_I2C3 = 138,
282 CCGR_I2C4 = 139,
283 CCGR_SAI1 = 140,
284 CCGR_SAI2 = 141,
285 CCGR_SAI3 = 142,
286 CCGR_SIM1 = 144,
287 CCGR_SIM2 = 145,
288 CCGR_UART1 = 148,
289 CCGR_UART2 = 149,
290 CCGR_UART3 = 150,
291 CCGR_UART4 = 151,
292 CCGR_UART5 = 152,
293 CCGR_UART6 = 153,
294 CCGR_UART7 = 154,
295 CCGR_WDOG1 = 156,
296 CCGR_WDOG2 = 157,
297 CCGR_WDOG3 = 158,
298 CCGR_WDOG4 = 159,
299 CCGR_GPIO1 = 160,
300 CCGR_GPIO2 = 161,
301 CCGR_GPIO3 = 162,
302 CCGR_GPIO4 = 163,
303 CCGR_GPIO5 = 164,
304 CCGR_GPIO6 = 165,
305 CCGR_GPIO7 = 166,
306 CCGR_IOMUX = 168,
307 CCGR_IOMUX_LPSR = 169,
308 CCGR_KPP = 170,
309
310 CCGR_SKIP,
311 CCGR_MAX,
312};
313
314
315enum clk_root_type {
316 CCM_CORE_CHANNEL,
317 CCM_BUS_CHANNEL,
318 CCM_AHB_CHANNEL,
319 CCM_DRAM_PHYM_CHANNEL,
320 CCM_DRAM_CHANNEL,
321 CCM_IP_CHANNEL,
322};
323
324#include <asm/arch/clock_slice.h>
325
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327
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329
330
331struct clk_root_map {
332 enum clk_root_index entry;
333 enum clk_root_type type;
334 uint8_t src_mux[8];
335};
336
337enum enet_freq {
338 ENET_25MHZ,
339 ENET_50MHZ,
340 ENET_125MHZ,
341};
342
343u32 get_root_clk(enum clk_root_index clock_id);
344u32 mxc_get_clock(enum mxc_clock clk);
345u32 imx_get_uartclk(void);
346u32 imx_get_fecclk(void);
347void clock_init(void);
348#ifdef CONFIG_SYS_I2C_MXC
349int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
350#endif
351#ifdef CONFIG_FEC_MXC
352int set_clk_enet(enum enet_freq type);
353#endif
354int set_clk_qspi(void);
355int set_clk_nand(void);
356#ifdef CONFIG_MXC_OCOTP
357void enable_ocotp_clk(unsigned char enable);
358#endif
359void enable_usboh3_clk(unsigned char enable);
360#ifdef CONFIG_SECURE_BOOT
361void hab_caam_clock_enable(unsigned char enable);
362#endif
363void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
364void enable_thermal_clk(void);
365#endif
366
