1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2007-2011 4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5 * Tom Cubie <tangliang@allwinnertech.com> 6 */ 7 8#ifndef _SUNXI_CPU_SUN4I_H 9#define _SUNXI_CPU_SUN4I_H 10 11#define SUNXI_SRAM_A1_BASE 0x00000000 12#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ 13 14#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ 15#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ 16#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ 17#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ 18#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ 19 20#define SUNXI_DE2_BASE 0x01000000 21 22#ifdef CONFIG_MACH_SUN8I_A83T 23#define SUNXI_CPUCFG_BASE 0x01700000 24#endif 25 26#define SUNXI_SRAMC_BASE 0x01c00000 27#define SUNXI_DRAMC_BASE 0x01c01000 28#define SUNXI_DMA_BASE 0x01c02000 29#define SUNXI_NFC_BASE 0x01c03000 30#define SUNXI_TS_BASE 0x01c04000 31#define SUNXI_SPI0_BASE 0x01c05000 32#define SUNXI_SPI1_BASE 0x01c06000 33#define SUNXI_MS_BASE 0x01c07000 34#define SUNXI_TVD_BASE 0x01c08000 35#define SUNXI_CSI0_BASE 0x01c09000 36#ifndef CONFIG_MACH_SUNXI_H3_H5 37#define SUNXI_TVE0_BASE 0x01c0a000 38#endif 39#define SUNXI_EMAC_BASE 0x01c0b000 40#define SUNXI_LCD0_BASE 0x01c0C000 41#define SUNXI_LCD1_BASE 0x01c0d000 42#define SUNXI_VE_BASE 0x01c0e000 43#define SUNXI_MMC0_BASE 0x01c0f000 44#define SUNXI_MMC1_BASE 0x01c10000 45#define SUNXI_MMC2_BASE 0x01c11000 46#define SUNXI_MMC3_BASE 0x01c12000 47#ifdef CONFIG_SUNXI_GEN_SUN4I 48#define SUNXI_USB0_BASE 0x01c13000 49#define SUNXI_USB1_BASE 0x01c14000 50#endif 51#define SUNXI_SS_BASE 0x01c15000 52#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) 53#define SUNXI_HDMI_BASE 0x01c16000 54#endif 55#define SUNXI_SPI2_BASE 0x01c17000 56#define SUNXI_SATA_BASE 0x01c18000 57#ifdef CONFIG_SUNXI_GEN_SUN4I 58#define SUNXI_PATA_BASE 0x01c19000 59#define SUNXI_ACE_BASE 0x01c1a000 60#define SUNXI_TVE1_BASE 0x01c1b000 61#define SUNXI_USB2_BASE 0x01c1c000 62#endif 63#ifdef CONFIG_SUNXI_GEN_SUN6I 64#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) 65#define SUNXI_USBPHY_BASE 0x01c19000 66#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE 67#define SUNXI_USB1_BASE 0x01c1a000 68#define SUNXI_USB2_BASE 0x01c1b000 69#define SUNXI_USB3_BASE 0x01c1c000 70#define SUNXI_USB4_BASE 0x01c1d000 71#else 72#define SUNXI_USB0_BASE 0x01c19000 73#define SUNXI_USB1_BASE 0x01c1a000 74#define SUNXI_USB2_BASE 0x01c1b000 75#endif 76#endif 77#define SUNXI_CSI1_BASE 0x01c1d000 78#define SUNXI_TZASC_BASE 0x01c1e000 79#define SUNXI_SPI3_BASE 0x01c1f000 80 81#define SUNXI_CCM_BASE 0x01c20000 82#define SUNXI_INTC_BASE 0x01c20400 83#define SUNXI_PIO_BASE 0x01c20800 84#define SUNXI_TIMER_BASE 0x01c20c00 85#ifndef CONFIG_SUNXI_GEN_SUN6I 86#define SUNXI_PWM_BASE 0x01c20e00 87#endif 88#define SUNXI_SPDIF_BASE 0x01c21000 89#ifdef CONFIG_SUNXI_GEN_SUN6I 90#define SUNXI_PWM_BASE 0x01c21400 91#else 92#define SUNXI_AC97_BASE 0x01c21400 93#endif 94#define SUNXI_IR0_BASE 0x01c21800 95#define SUNXI_IR1_BASE 0x01c21c00 96 97#define SUNXI_IIS_BASE 0x01c22400 98#define SUNXI_LRADC_BASE 0x01c22800 99#define SUNXI_AD_DA_BASE 0x01c22c00 100#define SUNXI_KEYPAD_BASE 0x01c23000 101#define SUNXI_TZPC_BASE 0x01c23400 102 103#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ 104defined(CONFIG_MACH_SUN50I) 105/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ 106#define SUNXI_SIDC_BASE 0x01c14000 107#define SUNXI_SID_BASE 0x01c14200 108#else 109#define SUNXI_SID_BASE 0x01c23800 110#endif 111 112#define SUNXI_SJTAG_BASE 0x01c23c00 113 114#define SUNXI_TP_BASE 0x01c25000 115#define SUNXI_PMU_BASE 0x01c25400 116 117#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40 118#define SUNXI_CPUCFG_BASE 0x01c25c00 119#endif 120 121#define SUNXI_UART0_BASE 0x01c28000 122#define SUNXI_UART1_BASE 0x01c28400 123#define SUNXI_UART2_BASE 0x01c28800 124#define SUNXI_UART3_BASE 0x01c28c00 125#define SUNXI_UART4_BASE 0x01c29000 126#define SUNXI_UART5_BASE 0x01c29400 127#define SUNXI_UART6_BASE 0x01c29800 128#define SUNXI_UART7_BASE 0x01c29c00 129#define SUNXI_PS2_0_BASE 0x01c2a000 130#define SUNXI_PS2_1_BASE 0x01c2a400 131 132#define SUNXI_TWI0_BASE 0x01c2ac00 133#define SUNXI_TWI1_BASE 0x01c2b000 134#define SUNXI_TWI2_BASE 0x01c2b400 135#ifdef CONFIG_MACH_SUN6I 136#define SUNXI_TWI3_BASE 0x01c0b800 137#endif 138#ifdef CONFIG_MACH_SUN7I 139#define SUNXI_TWI3_BASE 0x01c2b800 140#define SUNXI_TWI4_BASE 0x01c2c000 141#endif 142 143#define SUNXI_CAN_BASE 0x01c2bc00 144 145#define SUNXI_SCR_BASE 0x01c2c400 146 147#ifndef CONFIG_MACH_SUN6I 148#define SUNXI_GPS_BASE 0x01c30000 149#define SUNXI_MALI400_BASE 0x01c40000 150#define SUNXI_GMAC_BASE 0x01c50000 151#else 152#define SUNXI_GMAC_BASE 0x01c30000 153#endif 154 155#define SUNXI_DRAM_COM_BASE 0x01c62000 156#define SUNXI_DRAM_CTL0_BASE 0x01c63000 157#define SUNXI_DRAM_CTL1_BASE 0x01c64000 158#define SUNXI_DRAM_PHY0_BASE 0x01c65000 159#define SUNXI_DRAM_PHY1_BASE 0x01c66000 160 161#define SUNXI_GIC400_BASE 0x01c80000 162 163/* module sram */ 164#define SUNXI_SRAM_C_BASE 0x01d00000 165 166#ifndef CONFIG_MACH_SUN8I_H3 167#define SUNXI_DE_FE0_BASE 0x01e00000 168#else 169#define SUNXI_TVE0_BASE 0x01e00000 170#endif 171#define SUNXI_DE_FE1_BASE 0x01e20000 172#define SUNXI_DE_BE0_BASE 0x01e60000 173#ifndef CONFIG_MACH_SUN50I_H5 174#define SUNXI_DE_BE1_BASE 0x01e40000 175#else 176#define SUNXI_TVE0_BASE 0x01e40000 177#endif 178#define SUNXI_MP_BASE 0x01e80000 179#define SUNXI_AVG_BASE 0x01ea0000 180 181#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) 182#define SUNXI_HDMI_BASE 0x01ee0000 183#endif 184 185#define SUNXI_RTC_BASE 0x01f00000 186#define SUNXI_PRCM_BASE 0x01f01400 187 188#if defined CONFIG_SUNXI_GEN_SUN6I && \ 189 !defined CONFIG_MACH_SUN8I_A83T && \ 190 !defined CONFIG_MACH_SUN8I_R40 191#define SUNXI_CPUCFG_BASE 0x01f01c00 192#endif 193 194#define SUNXI_R_TWI_BASE 0x01f02400 195#define SUNXI_R_UART_BASE 0x01f02800 196#define SUNXI_R_PIO_BASE 0x01f02c00 197#define SUN6I_P2WI_BASE 0x01f03400 198#define SUNXI_RSB_BASE 0x01f03400 199 200/* CoreSight Debug Module */ 201#define SUNXI_CSDM_BASE 0x3f500000 202 203#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ 204 205#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ 206 207#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 208 209/* SS bonding ids used for cpu identification */ 210#define SUNXI_SS_BOND_ID_A31 4 211#define SUNXI_SS_BOND_ID_A31S 5 212 213#ifndef __ASSEMBLY__ 214void sunxi_board_init(void); 215void sunxi_reset(void); 216int sunxi_get_ss_bonding_id(void); 217int sunxi_get_sid(unsigned int *sid); 218#endif /* __ASSEMBLY__ */ 219 220#endif /* _SUNXI_CPU_SUN4I_H */ 221