LXR uboot/arch/arm/mach-at91/arm926ejs/timer.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007-2008
   4 * Stelian Pop <stelian@popies.net>
   5 * Lead Tech Design <www.leadtechdesign.com>
   6 */
   7
   8#include <common.h>
   9#include <asm/io.h>
  10#include <asm/arch/hardware.h>
  11#include <asm/arch/at91_pit.h>
  12#include <asm/arch/clk.h>
  13#include <div64.h>
  14
  15#if !defined(CONFIG_AT91FAMILY)
  16# error You need to define CONFIG_AT91FAMILY in your board config!
  17#endif
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21/*
  22 * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  23 * setting the 20 bit counter period to its maximum (0xfffff).
  24 * (See the relevant data sheets to understand that this really works)
  25 *
  26 * We do also mimic the typical powerpc way of incrementing
  27 * two 32 bit registers called tbl and tbu.
  28 *
  29 * Those registers increment at 1/16 the main clock rate.
  30 */
  31
  32#define TIMER_LOAD_VAL  0xfffff
  33
  34/*
  35 * Use the PITC in full 32 bit incrementing mode
  36 */
  37int timer_init(void)
  38{
  39        at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
  40
  41        at91_periph_clk_enable(ATMEL_ID_SYS);
  42
  43        /* Enable PITC */
  44        writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  45
  46        gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
  47
  48        return 0;
  49}
  50
  51/*
  52 * Return the number of timer ticks per second.
  53 */
  54ulong get_tbclk(void)
  55{
  56        return gd->arch.timer_rate_hz;
  57}
  58