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13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H
15
16#include <linux/sizes.h>
17
18#define REG(addr) (*(volatile unsigned int *)(addr))
19#define REG_P(addr) ((volatile unsigned int *)(addr))
20
21#ifndef __ASSEMBLY__
22typedef volatile unsigned int dv_reg;
23typedef volatile unsigned int * dv_reg_p;
24#endif
25
26#define DAVINCI_UART0_BASE 0x01c42000
27#define DAVINCI_UART1_BASE 0x01d0c000
28#define DAVINCI_UART2_BASE 0x01d0d000
29#define DAVINCI_I2C0_BASE 0x01c22000
30#define DAVINCI_I2C1_BASE 0x01e28000
31#define DAVINCI_TIMER0_BASE 0x01c20000
32#define DAVINCI_TIMER1_BASE 0x01c21000
33#define DAVINCI_WDOG_BASE 0x01c21000
34#define DAVINCI_RTC_BASE 0x01c23000
35#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
36#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
37#define DAVINCI_PSC0_BASE 0x01c10000
38#define DAVINCI_PSC1_BASE 0x01e27000
39#define DAVINCI_SPI0_BASE 0x01c41000
40#define DAVINCI_USB_OTG_BASE 0x01e00000
41#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
42 0x01e12000 : 0x01f0e000)
43#define DAVINCI_GPIO_BASE 0x01e26000
44#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
45#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
46#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
47#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
48#define DAVINCI_SYSCFG1_BASE 0x01e2c000
49#define DAVINCI_MMC_SD0_BASE 0x01c40000
50#define DAVINCI_MMC_SD1_BASE 0x01e1b000
51#define DAVINCI_TIMER2_BASE 0x01f0c000
52#define DAVINCI_TIMER3_BASE 0x01f0d000
53#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
54#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
55#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
56#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
57#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
58#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
59#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
60#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
61#define DAVINCI_INTC_BASE 0xfffee000
62#define DAVINCI_BOOTCFG_BASE 0x01c14000
63#define DAVINCI_LCD_CNTL_BASE 0x01e13000
64#define DAVINCI_L3CBARAM_BASE 0x80000000
65#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
66#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
67#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
68#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
69
70#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
71#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
72#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
73#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
74#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
75#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
76#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
77#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
78#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
79#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
80#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
81#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
82
83
84#define DAVINCI_GPSC_ARMDOMAIN 0
85#define DAVINCI_GPSC_DSPDOMAIN 1
86
87#define DAVINCI_LPSC_TPCC 0
88#define DAVINCI_LPSC_TPTC0 1
89#define DAVINCI_LPSC_TPTC1 2
90#define DAVINCI_LPSC_AEMIF 3
91#define DAVINCI_LPSC_SPI0 4
92#define DAVINCI_LPSC_MMC_SD 5
93#define DAVINCI_LPSC_AINTC 6
94#define DAVINCI_LPSC_ARM_RAM_ROM 7
95#define DAVINCI_LPSC_SECCTL_KEYMGR 8
96#define DAVINCI_LPSC_UART0 9
97#define DAVINCI_LPSC_SCR0 10
98#define DAVINCI_LPSC_SCR1 11
99#define DAVINCI_LPSC_SCR2 12
100#define DAVINCI_LPSC_DMAX 13
101#define DAVINCI_LPSC_ARM 14
102#define DAVINCI_LPSC_GEM 15
103
104
105#define DAVINCI_LPSC_PSC1_BASE 32
106#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
107#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
108#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
109#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
110#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
111#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
112#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
113#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
114#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
115#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
116#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
117#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
118#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
119#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
120#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
121#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
122
123
124#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
125#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
126#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
127#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
128#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
129#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
130
131
132#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
133#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
134#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
135#define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
136#define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
137#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
138#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
139#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
140#define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
141#define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
142#define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
143#define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
144#define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
145#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
146#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
147
148#ifndef __ASSEMBLY__
149void lpsc_on(unsigned int id);
150void lpsc_syncreset(unsigned int id);
151void lpsc_disable(unsigned int id);
152void dsp_on(void);
153
154void davinci_enable_uart0(void);
155void davinci_enable_emac(void);
156void davinci_enable_i2c(void);
157void davinci_errata_workarounds(void);
158
159#define PSC_ENABLE 0x3
160#define PSC_DISABLE 0x2
161#define PSC_SYNCRESET 0x1
162#define PSC_SWRSTDISABLE 0x0
163
164#define PSC_PSC0_MODULE_ID_CNT 16
165#define PSC_PSC1_MODULE_ID_CNT 32
166
167#define UART0_PWREMU_MGMT (0x01c42030)
168
169struct davinci_psc_regs {
170 dv_reg revid;
171 dv_reg rsvd0[71];
172 dv_reg ptcmd;
173 dv_reg rsvd1;
174 dv_reg ptstat;
175 dv_reg rsvd2[437];
176 union {
177 struct {
178 dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
179 dv_reg rsvd3[112];
180 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
181 } psc0;
182 struct {
183 dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
184 dv_reg rsvd3[96];
185 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
186 } psc1;
187 };
188};
189
190#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
191#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
192
193#define PSC_MDSTAT_STATE 0x3f
194#define PSC_MDCTL_NEXT 0x07
195
196struct davinci_pllc_regs {
197 dv_reg revid;
198 dv_reg rsvd1[56];
199 dv_reg rstype;
200 dv_reg rsvd2[6];
201 dv_reg pllctl;
202 dv_reg ocsel;
203 dv_reg rsvd3[2];
204 dv_reg pllm;
205 dv_reg prediv;
206 dv_reg plldiv1;
207 dv_reg plldiv2;
208 dv_reg plldiv3;
209 dv_reg oscdiv;
210 dv_reg postdiv;
211 dv_reg rsvd4[3];
212 dv_reg pllcmd;
213 dv_reg pllstat;
214 dv_reg alnctl;
215 dv_reg dchange;
216 dv_reg cken;
217 dv_reg ckstat;
218 dv_reg systat;
219 dv_reg rsvd5[3];
220 dv_reg plldiv4;
221 dv_reg plldiv5;
222 dv_reg plldiv6;
223 dv_reg plldiv7;
224 dv_reg rsvd6[32];
225 dv_reg emucnt0;
226 dv_reg emucnt1;
227};
228
229#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
230#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
231#define DAVINCI_PLLC_DIV_MASK 0x1f
232
233
234
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237
238
239
240#define DAVINCI_PLLC0_FLAG (0)
241#define DAVINCI_PLLC1_FLAG (1 << 16)
242
243enum davinci_clk_ids {
244
245
246
247
248 DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2,
249 DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4,
250 DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6,
251 DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1,
252 DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
253
254
255 DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
256 DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
257 DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
258 DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
259 DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
260 DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2,
261
262
263 DAVINCI_PLLM_CLKID = 0x0FF,
264
265
266 DAVINCI_PLLC_CLKID = 0x100,
267
268
269 DAVINCI_AUXCLK_CLKID = 0x101,
270};
271
272#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
273 : get_async3_src())
274
275#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
276 : get_async3_src())
277
278int clk_get(enum davinci_clk_ids id);
279
280
281struct davinci_syscfg_regs {
282 dv_reg revid;
283 dv_reg rsvd[7];
284 dv_reg bootcfg;
285 dv_reg chiprevidr;
286 dv_reg rsvd2[4];
287 dv_reg kick0;
288 dv_reg kick1;
289 dv_reg rsvd1[52];
290 dv_reg mstpri[3];
291 dv_reg rsvd3;
292 dv_reg pinmux[20];
293 dv_reg suspsrc;
294 dv_reg chipsig;
295 dv_reg chipsig_clr;
296 dv_reg cfgchip0;
297 dv_reg cfgchip1;
298 dv_reg cfgchip2;
299 dv_reg cfgchip3;
300 dv_reg cfgchip4;
301};
302
303#define davinci_syscfg_regs \
304 ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
305
306enum {
307 DAVINCI_NAND8_BOOT = 0b001110,
308 DAVINCI_NAND16_BOOT = 0b010000,
309 DAVINCI_SD_OR_MMC_BOOT = 0b011100,
310 DAVINCI_MMC_ONLY_BOOT = 0b111100,
311 DAVINCI_SPI0_FLASH_BOOT = 0b001010,
312 DAVINCI_SPI1_FLASH_BOOT = 0b001100,
313};
314
315#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
316
317
318#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
319#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
320#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
321#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
322#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
323#define DAVINCI_SYSCFG_SUSPSRC_UART1 (1 << 19)
324#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
325#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
326
327struct davinci_syscfg1_regs {
328 dv_reg vtpio_ctl;
329 dv_reg ddr_slew;
330 dv_reg deepsleep;
331 dv_reg pupd_ena;
332 dv_reg pupd_sel;
333 dv_reg rxactive;
334 dv_reg pwrdwn;
335};
336
337#define davinci_syscfg1_regs \
338 ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
339
340#define DDR_SLEW_CMOSEN_BIT 4
341#define DDR_SLEW_DDR_PDENA_BIT 5
342
343#define VTP_POWERDWN (1 << 6)
344#define VTP_LOCK (1 << 7)
345#define VTP_CLKRZ (1 << 13)
346#define VTP_READY (1 << 15)
347#define VTP_IOPWRDWN (1 << 14)
348
349#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
350#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
351
352
353struct davinci_aintc_regs {
354 dv_reg revid;
355 dv_reg cr;
356 dv_reg dummy0[2];
357 dv_reg ger;
358 dv_reg dummy1[219];
359 dv_reg ecr1;
360 dv_reg ecr2;
361 dv_reg ecr3;
362 dv_reg dummy2[1117];
363 dv_reg hier;
364};
365
366#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
367
368struct davinci_uart_ctrl_regs {
369 dv_reg revid1;
370 dv_reg revid2;
371 dv_reg pwremu_mgmt;
372 dv_reg mdr;
373};
374
375#define DAVINCI_UART_CTRL_BASE 0x28
376#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
377#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
378#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
379
380#define davinci_uart0_ctrl_regs \
381 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
382#define davinci_uart1_ctrl_regs \
383 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
384#define davinci_uart2_ctrl_regs \
385 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
386
387
388#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
389#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
390#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
391
392static inline int cpu_is_da830(void)
393{
394 unsigned int jtag_id = REG(JTAG_ID_REG);
395 unsigned short part_no = (jtag_id >> 12) & 0xffff;
396
397 return ((part_no == 0xb7df) ? 1 : 0);
398}
399static inline int cpu_is_da850(void)
400{
401 unsigned int jtag_id = REG(JTAG_ID_REG);
402 unsigned short part_no = (jtag_id >> 12) & 0xffff;
403
404 return ((part_no == 0xb7d1) ? 1 : 0);
405}
406
407static inline enum davinci_clk_ids get_async3_src(void)
408{
409 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
410 DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
411}
412
413#endif
414
415#endif
416
