LXR uboot/arch/arm/mach-omap2/omap5/emif.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * EMIF programming
   4 *
   5 * (C) Copyright 2010
   6 * Texas Instruments, <www.ti.com>
   7 *
   8 * Aneesh V <aneesh@ti.com> for OMAP4
   9 */
  10
  11#include <common.h>
  12#include <asm/emif.h>
  13#include <asm/arch/sys_proto.h>
  14#include <asm/utils.h>
  15
  16#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  17#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
  18static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
  19static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
  20#endif
  21
  22#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
  23/* Base AC Timing values specified by JESD209-2 for 532MHz operation */
  24static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
  25        .max_freq = 532000000,
  26        .RL = 8,
  27        .tRPab = 21,
  28        .tRCD = 18,
  29        .tWR = 15,
  30        .tRASmin = 42,
  31        .tRRD = 10,
  32        .tWTRx2 = 15,
  33        .tXSR = 140,
  34        .tXPx2 = 15,
  35        .tRFCab = 130,
  36        .tRTPx2 = 15,
  37        .tCKE = 3,
  38        .tCKESR = 15,
  39        .tZQCS = 90,
  40        .tZQCL = 360,
  41        .tZQINIT = 1000,
  42        .tDQSCKMAXx2 = 11,
  43        .tRASmax = 70,
  44        .tFAW = 50
  45};
  46
  47/*
  48 * Min tCK values specified by JESD209-2
  49 * Min tCK specifies the minimum duration of some AC timing parameters in terms
  50 * of the number of cycles. If the calculated number of cycles based on the
  51 * absolute time value is less than the min tCK value, min tCK value should
  52 * be used instead. This typically happens at low frequencies.
  53 */
  54static const struct lpddr2_min_tck min_tck_jedec = {
  55        .tRL = 3,
  56        .tRP_AB = 3,
  57        .tRCD = 3,
  58        .tWR = 3,
  59        .tRAS_MIN = 3,
  60        .tRRD = 2,
  61        .tWTR = 2,
  62        .tXP = 2,
  63        .tRTP = 2,
  64        .tCKE = 3,
  65        .tCKESR = 3,
  66        .tFAW = 8
  67};
  68
  69static const struct lpddr2_ac_timings const*
  70                        jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
  71        &timings_jedec_532_mhz
  72};
  73
  74static const struct lpddr2_device_timings jedec_default_timings = {
  75        .ac_timings = jedec_ac_timings,
  76        .min_tck = &min_tck_jedec
  77};
  78
  79void emif_get_device_timings(u32 emif_nr,
  80                const struct lpddr2_device_timings **cs0_device_timings,
  81                const struct lpddr2_device_timings **cs1_device_timings)
  82{
  83        /* Assume Identical devices on EMIF1 & EMIF2 */
  84        *cs0_device_timings = &jedec_default_timings;
  85        *cs1_device_timings = NULL;
  86}
  87#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
  88