LXR uboot/arch/arm/mach-socfpga/reset_manager

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   4 */
   5
   6
   7#include <common.h>
   8#include <asm/io.h>
   9#include <asm/arch/fpga_manager.h>
  10#include <asm/arch/reset_manager.h>
  11#include <asm/arch/system_manager.h>
  12
  13static const struct socfpga_reset_manager *reset_manager_base =
  14                (void *)SOCFPGA_RSTMGR_ADDRESS;
  15static const struct socfpga_system_manager *sysmgr_regs =
  16        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  17
  18/* Assert or de-assert SoCFPGA reset manager reset. */
  19void socfpga_per_reset(u32 reset, int set)
  20{
  21        const u32 *reg;
  22        u32 rstmgr_bank = RSTMGR_BANK(reset);
  23
  24        switch (rstmgr_bank) {
  25        case 0:
  26                reg = &reset_manager_base->mpu_mod_reset;
  27                break;
  28        case 1:
  29                reg = &reset_manager_base->per_mod_reset;
  30                break;
  31        case 2:
  32                reg = &reset_manager_base->per2_mod_reset;
  33                break;
  34        case 3:
  35                reg = &reset_manager_base->brg_mod_reset;
  36                break;
  37        case 4:
  38                reg = &reset_manager_base->misc_mod_reset;
  39                break;
  40
  41        default:
  42                return;
  43        }
  44
  45        if (set)
  46                setbits_le32(reg, 1 << RSTMGR_RESET(reset));
  47        else
  48                clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
  49}
  50
  51/*
  52 * Assert reset on every peripheral but L4WD0.
  53 * Watchdog must be kept intact to prevent glitches
  54 * and/or hangs.
  55 */
  56void socfpga_per_reset_all(void)
  57{
  58        const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  59
  60        writel(~l4wd0, &reset_manager_base->per_mod_reset);
  61        writel(0xffffffff, &reset_manager_base->per2_mod_reset);
  62}
  63
  64#define L3REGS_REMAP_LWHPS2FPGA_MASK    0x10
  65#define L3REGS_REMAP_HPS2FPGA_MASK      0x08
  66#define L3REGS_REMAP_OCRAM_MASK         0x01
  67
  68void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
  69{
  70        u32 brgmask = 0x0;
  71        u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
  72
  73        if (h2f)
  74                brgmask |= BIT(0);
  75        else
  76                l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
  77
  78        if (lwh2f)
  79                brgmask |= BIT(1);
  80        else
  81                l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
  82
  83        if (f2h)
  84                brgmask |= BIT(2);
  85
  86        writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
  87        writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
  88}
  89
  90void socfpga_bridges_reset(int enable)
  91{
  92        const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
  93                                L3REGS_REMAP_HPS2FPGA_MASK |
  94                                L3REGS_REMAP_OCRAM_MASK;
  95
  96        if (enable) {
  97                /* brdmodrst */
  98                writel(0x7, &reset_manager_base->brg_mod_reset);
  99                writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
 100        } else {
 101                socfpga_bridges_set_handoff_regs(false, false, false);
 102
 103                /* Check signal from FPGA. */
 104                if (!fpgamgr_test_fpga_ready()) {
 105                        /* FPGA not ready, do nothing. We allow system to boot
 106                         * without FPGA ready. So, return 0 instead of error. */
 107                        printf("%s: FPGA not ready, aborting.\n", __func__);
 108                        return;
 109                }
 110
 111                /* brdmodrst */
 112                writel(0, &reset_manager_base->brg_mod_reset);
 113
 114                /* Remap the bridges into memory map */
 115                writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
 116        }
 117        return;
 118}
 119