LXR uboot/arch/arm/mach-uniphier/clk/dpll-ld4.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2013-2014 Panasonic Corporation
   4 * Copyright (C) 2015-2016 Socionext Inc.
   5 */
   6
   7#include <common.h>
   8#include <linux/errno.h>
   9#include <linux/io.h>
  10
  11#include "../init.h"
  12#include "../sc-regs.h"
  13
  14#undef DPLL_SSC_RATE_1PER
  15
  16int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
  17{
  18        unsigned int dram_freq = bd->dram_freq;
  19        u32 tmp;
  20
  21        /*
  22         * Set Frequency
  23         * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
  24         * to FOUT (DPLLCTRL.bit[29:20])
  25         */
  26        tmp = readl(SC_DPLLCTRL);
  27        tmp &= ~0x000f0000;
  28        switch (dram_freq) {
  29        case 1333:
  30                tmp |= 0x000d0000;
  31                break;
  32        case 1600:
  33                tmp |= 0x000c0000;
  34                break;
  35        default:
  36                pr_err("Unsupported frequency");
  37                return -EINVAL;
  38        }
  39
  40#if defined(DPLL_SSC_RATE_1PER)
  41        tmp &= ~SC_DPLLCTRL_SSC_RATE;
  42#else
  43        tmp |= SC_DPLLCTRL_SSC_RATE;
  44#endif
  45        writel(tmp, SC_DPLLCTRL);
  46
  47        tmp = readl(SC_DPLLCTRL2);
  48        tmp |= SC_DPLLCTRL2_NRSTDS;
  49        writel(tmp, SC_DPLLCTRL2);
  50
  51        /* Wait 500 usec until dpll gets stable */
  52        udelay(500);
  53
  54        return 0;
  55}
  56