LXR uboot/arch/x86/cpu/baytrail/early

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2015 Google, Inc
   4 */
   5
   6#include <common.h>
   7#include <errno.h>
   8#include <asm/io.h>
   9
  10#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
  11                (((segbus) & 0xfff) << 20) | \
  12                (((dev) & 0x1f) << 15) | \
  13                (((fn)  & 0x07) << 12))
  14
  15/* Platform Controller Unit */
  16#define LPC_DEV                 0x1f
  17#define LPC_FUNC                0
  18
  19/* Enable UART */
  20#define UART_CONT               0x80
  21
  22/* SCORE Pad definitions */
  23#define UART_RXD_PAD                    82
  24#define UART_TXD_PAD                    83
  25
  26/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
  27#define GPSCORE_PAD_BASE        (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
  28
  29/* IO Memory */
  30#define IO_BASE_ADDRESS                 0xfed0c000
  31#define  IO_BASE_OFFSET_GPSCORE         0x0000
  32#define  IO_BASE_OFFSET_GPNCORE         0x1000
  33#define  IO_BASE_OFFSET_GPSSUS          0x2000
  34#define IO_BASE_SIZE                    0x4000
  35
  36static inline unsigned int score_pconf0(int pad_num)
  37{
  38        return GPSCORE_PAD_BASE + pad_num * 16;
  39}
  40
  41static void score_select_func(int pad, int func)
  42{
  43        uint32_t reg;
  44        uint32_t pconf0_addr = score_pconf0(pad);
  45
  46        reg = readl(pconf0_addr);
  47        reg &= ~0x7;
  48        reg |= func & 0x7;
  49        writel(reg, pconf0_addr);
  50}
  51
  52static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
  53{
  54        unsigned long addr;
  55
  56        addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
  57        writel(value, addr);
  58}
  59
  60/* This can be called after memory-mapped PCI is working */
  61int setup_internal_uart(int enable)
  62{
  63        /* Enable or disable the legacy UART hardware */
  64        x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
  65                               enable);
  66
  67        /* All done for the disable part, so just return */
  68        if (!enable)
  69                return 0;
  70
  71        /*
  72         * Set up the pads to the UART function. This allows the signals to
  73         * leave the chip
  74         */
  75        score_select_func(UART_RXD_PAD, 1);
  76        score_select_func(UART_TXD_PAD, 1);
  77
  78        /* TODO(sjg@chromium.org): Call debug_uart_init() */
  79
  80        return 0;
  81}
  82
  83void board_debug_uart_init(void)
  84{
  85        setup_internal_uart(1);
  86}
  87