1
2
3
4
5
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/sama5d3_smc.h>
10#include <asm/arch/at91_common.h>
11#include <asm/arch/at91_rstc.h>
12#include <asm/arch/gpio.h>
13#include <asm/arch/clk.h>
14#include <debug_uart.h>
15#include <spl.h>
16#include <asm/arch/atmel_mpddrc.h>
17#include <asm/arch/at91_wdt.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21extern void at91_pda_detect(void);
22
23#ifdef CONFIG_NAND_ATMEL
24void sama5d3_xplained_nand_hw_init(void)
25{
26 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
27
28 at91_periph_clk_enable(ATMEL_ID_SMC);
29
30
31 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
32 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
33 &smc->cs[3].setup);
34 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
35 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
36 &smc->cs[3].pulse);
37 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
38 &smc->cs[3].cycle);
39 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
40 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
41 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
42 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
43 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
44 AT91_SMC_MODE_EXNW_DISABLE |
45#ifdef CONFIG_SYS_NAND_DBW_16
46 AT91_SMC_MODE_DBW_16 |
47#else
48 AT91_SMC_MODE_DBW_8 |
49#endif
50 AT91_SMC_MODE_TDF_CYCLE(3),
51 &smc->cs[3].mode);
52}
53#endif
54
55#ifdef CONFIG_CMD_USB
56static void sama5d3_xplained_usb_hw_init(void)
57{
58 at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
59 at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
60}
61#endif
62
63#ifdef CONFIG_GENERIC_ATMEL_MCI
64static void sama5d3_xplained_mci0_hw_init(void)
65{
66 at91_set_pio_output(AT91_PIO_PORTE, 2, 0);
67}
68#endif
69
70#ifdef CONFIG_DEBUG_UART_BOARD_INIT
71void board_debug_uart_init(void)
72{
73 at91_seriald_hw_init();
74}
75#endif
76
77#ifdef CONFIG_BOARD_LATE_INIT
78int board_late_init(void)
79{
80 at91_pda_detect();
81 return 0;
82}
83#endif
84
85#ifdef CONFIG_BOARD_EARLY_INIT_F
86int board_early_init_f(void)
87{
88#ifdef CONFIG_DEBUG_UART
89 debug_uart_init();
90#endif
91 return 0;
92}
93#endif
94
95int board_init(void)
96{
97
98 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
99
100#ifdef CONFIG_NAND_ATMEL
101 sama5d3_xplained_nand_hw_init();
102#endif
103#ifdef CONFIG_CMD_USB
104 sama5d3_xplained_usb_hw_init();
105#endif
106#ifdef CONFIG_GENERIC_ATMEL_MCI
107 sama5d3_xplained_mci0_hw_init();
108#endif
109 return 0;
110}
111
112int dram_init(void)
113{
114 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
115 CONFIG_SYS_SDRAM_SIZE);
116
117 return 0;
118}
119
120
121#ifdef CONFIG_SPL_BUILD
122void spl_board_init(void)
123{
124#ifdef CONFIG_SD_BOOT
125#ifdef CONFIG_GENERIC_ATMEL_MCI
126 sama5d3_xplained_mci0_hw_init();
127#endif
128#elif CONFIG_NAND_BOOT
129 sama5d3_xplained_nand_hw_init();
130#endif
131}
132
133static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
134{
135 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
136
137 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
138 ATMEL_MPDDRC_CR_NR_ROW_14 |
139 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
140 ATMEL_MPDDRC_CR_ENRDM_ON |
141 ATMEL_MPDDRC_CR_NB_8BANKS |
142 ATMEL_MPDDRC_CR_NDQS_DISABLED |
143 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
144 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
145
146
147
148
149 ddr2->rtr = 0x411;
150
151 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
152 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
153 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
154 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
155 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
156 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
157 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
158 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
159
160 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
161 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
162 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
163 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
164
165 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
166 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
167 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
168 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
169 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
170}
171
172void mem_init(void)
173{
174 struct atmel_mpddrc_config ddr2;
175
176 ddr2_conf(&ddr2);
177
178
179 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
180 at91_system_clk_enable(AT91_PMC_DDR);
181
182
183 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
184}
185
186void at91_pmc_init(void)
187{
188 u32 tmp;
189
190 tmp = AT91_PMC_PLLAR_29 |
191 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
192 AT91_PMC_PLLXR_MUL(43) |
193 AT91_PMC_PLLXR_DIV(1);
194 at91_plla_init(tmp);
195
196 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
197
198 tmp = AT91_PMC_MCKR_MDIV_4 |
199 AT91_PMC_MCKR_CSS_PLLA;
200 at91_mck_init(tmp);
201}
202#endif
203
