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5
6#include <common.h>
7#include <fsl_ddr_sdram.h>
8
9#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
10#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
11#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
12#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
13#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
14#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
15#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
16#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
17
18#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
19#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
20#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
21#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
22#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
23#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
24#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
25#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
26
27#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
28#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
29#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
30#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
31#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
32#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
33#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
34#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
35
36#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
37#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
38#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
39#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
40#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
41#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
42#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
43#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
44
45#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
46#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
47#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
48#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
49#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
50#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
51#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
52#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
53#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
54#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
55#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
56#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
57#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
58#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
59#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
60#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
61#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
62#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
63#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
64#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
65#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
66#define CONFIG_SYS_DDR_TIMING_4 0x00000001
67#define CONFIG_SYS_DDR_TIMING_5 0x02401400
68#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
69#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
70#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
71#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
72#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
73#define CONFIG_SYS_DDR_RCW_1 0x00000000
74#define CONFIG_SYS_DDR_RCW_2 0x00000000
75#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
76
77fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
82 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
83 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
84 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
85 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
86 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
88 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
89 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
90 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
91 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
92 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
93 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
94 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
95 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
96 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
97 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
98 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
99 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
100 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
101 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
102 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
103 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
104 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
105 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
106 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
107};
108
109fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
110 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
111 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
112 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
113 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
114 .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
115 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
116 .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
117 .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
118 .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
120 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
121 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
122 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
123 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
124 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
125 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
126 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
127 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
128 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
129 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
130 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
131 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
132 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
133 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
134 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
135 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
136 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
137 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
138 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
139};
140
141fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
142 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
143 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
144 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
145 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
146 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
147 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
148 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
149 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
150 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
151 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
152 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
153 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
154 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
155 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
156 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
157 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
158 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
159 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
160 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
161 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
162 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
163 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
164 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
165 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
166 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
167 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
168 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
169 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
170 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
171};
172
173fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
174 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
175 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
176 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
177 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
178 .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
179 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
180 .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
181 .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
182 .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
183 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
184 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
185 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
186 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
187 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
188 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
189 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
190 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
191 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
192 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
193 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
194 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
195 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
196 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
197 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
198 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
199 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
200 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
201 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
202 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
203};
204
205fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
206 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
207 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
208 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
209 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
210 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
211 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
212 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
213 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
214 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
215 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
216 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
217 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
218 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
219 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
220 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
221 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
222 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
223 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
224 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
225 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
226 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
227 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
228 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
229 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
230 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
231 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
232 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
233 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
234 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
235};
236
237fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
238 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
239 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
240 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
241 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
242 .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
243 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
244 .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
245 .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
246 .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
247 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
248 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
249 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
250 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
251 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
252 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
253 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
254 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
255 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
256 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
257 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
258 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
259 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
260 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
261 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
262 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
263 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
264 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
265 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
266 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
267};
268
269fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
270 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
271 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
272 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
273 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
274 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
275 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
276 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
277 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
278 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
279 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
280 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
281 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
282 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
283 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
284 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
285 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
286 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
287 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
288 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
289 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
290 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
291 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
292 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
293 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
294 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
295 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
296 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
297 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
298 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
299};
300
301fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
302 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
303 .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
304 .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
305 .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
306 .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
307 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
308 .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
309 .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
310 .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
311 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
312 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
313 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
314 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
315 .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
316 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
317 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
318 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
319 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
320 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
321 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
322 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
323 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
324 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
325 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
326 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
327 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
328 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
329 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
330 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
331};
332
333fixed_ddr_parm_t fixed_ddr_parm_0[] = {
334 {750, 850, &ddr_cfg_regs_800},
335 {850, 950, &ddr_cfg_regs_900},
336 {950, 1050, &ddr_cfg_regs_1000},
337 {1050, 1250, &ddr_cfg_regs_1200},
338 {0, 0, NULL}
339};
340
341fixed_ddr_parm_t fixed_ddr_parm_1[] = {
342 {750, 850, &ddr_cfg_regs_800_2nd},
343 {850, 950, &ddr_cfg_regs_900_2nd},
344 {950, 1050, &ddr_cfg_regs_1000_2nd},
345 {1050, 1250, &ddr_cfg_regs_1200_2nd},
346 {0, 0, NULL}
347};
348
