LXR uboot/board/sbc8548/sbc8548.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
   4 *
   5 * Copyright 2007 Embedded Specialties, Inc.
   6 *
   7 * Copyright 2004, 2007 Freescale Semiconductor.
   8 *
   9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  10 */
  11
  12#include <common.h>
  13#include <pci.h>
  14#include <asm/processor.h>
  15#include <asm/immap_85xx.h>
  16#include <asm/fsl_pci.h>
  17#include <fsl_ddr_sdram.h>
  18#include <asm/fsl_serdes.h>
  19#include <spd_sdram.h>
  20#include <netdev.h>
  21#include <tsec.h>
  22#include <miiphy.h>
  23#include <linux/libfdt.h>
  24#include <fdt_support.h>
  25
  26void local_bus_init(void);
  27
  28int board_early_init_f (void)
  29{
  30        return 0;
  31}
  32
  33int checkboard (void)
  34{
  35        volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  36        volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
  37
  38        printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
  39                        in_8(rev) >> 4);
  40
  41        /*
  42         * Initialize local bus.
  43         */
  44        local_bus_init ();
  45
  46        out_be32(&ecm->eedr, 0xffffffff);       /* clear ecm errors */
  47        out_be32(&ecm->eeer, 0xffffffff);       /* enable ecm errors */
  48        return 0;
  49}
  50
  51/*
  52 * Initialize Local Bus
  53 */
  54void
  55local_bus_init(void)
  56{
  57        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  58        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  59
  60        uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
  61        sys_info_t sysinfo;
  62
  63        get_sys_info(&sysinfo);
  64
  65        lbc_mhz = sysinfo.freq_localbus / 1000000;
  66        clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
  67
  68        debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
  69
  70        out_be32(&gur->lbiuiplldcr1, 0x00078080);
  71        if (clkdiv == 16) {
  72                out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
  73        } else if (clkdiv == 8) {
  74                out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
  75        } else if (clkdiv == 4) {
  76                out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
  77        }
  78
  79        /*
  80         * Local Bus Clock > 83.3 MHz. According to timing
  81         * specifications set LCRR[EADC] to 2 delay cycles.
  82         */
  83        if (lbc_mhz > 83) {
  84                lcrr &= ~LCRR_EADC;
  85                lcrr |= LCRR_EADC_2;
  86        }
  87
  88        /*
  89         * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
  90         * disable PLL bypass for Local Bus Clock > 83 MHz.
  91         */
  92        if (lbc_mhz >= 66)
  93                lcrr &= (~LCRR_DBYP);   /* DLL Enabled */
  94
  95        else
  96                lcrr |= LCRR_DBYP;      /* DLL Bypass */
  97
  98        out_be32(&lbc->lcrr, lcrr);
  99        asm("sync;isync;msync");
 100
 101         /*
 102         * According to MPC8548ERMAD Rev.1.3 read back LCRR
 103         * and terminate with isync
 104         */
 105        lcrr = in_be32(&lbc->lcrr);
 106        asm ("isync;");
 107
 108        /* let DLL stabilize */
 109        udelay(500);
 110
 111        out_be32(&lbc->ltesr, 0xffffffff);      /* Clear LBC error IRQs */
 112        out_be32(&lbc->lteir, 0xffffffff);      /* Enable LBC error IRQs */
 113}
 114
 115/*
 116 * Initialize SDRAM memory on the Local Bus.
 117 */
 118void lbc_sdram_init(void)
 119{
 120#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 121
 122        uint idx;
 123        const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
 124        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 125        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 126        uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
 127
 128        puts("    SDRAM: ");
 129
 130        print_size(size, "\n");
 131
 132        /*
 133         * Setup SDRAM Base and Option Registers
 134         */
 135        set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 136        set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 137        set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
 138        set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
 139
 140        out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 141        asm("msync");
 142
 143        out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
 144        out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 145        asm("msync");
 146
 147        /*
 148         * Issue PRECHARGE ALL command.
 149         */
 150        out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
 151        asm("sync;msync");
 152        *sdram_addr = 0xff;
 153        ppcDcbf((unsigned long) sdram_addr);
 154        *sdram_addr2 = 0xff;
 155        ppcDcbf((unsigned long) sdram_addr2);
 156        udelay(100);
 157
 158        /*
 159         * Issue 8 AUTO REFRESH commands.
 160         */
 161        for (idx = 0; idx < 8; idx++) {
 162                out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
 163                asm("sync;msync");
 164                *sdram_addr = 0xff;
 165                ppcDcbf((unsigned long) sdram_addr);
 166                *sdram_addr2 = 0xff;
 167                ppcDcbf((unsigned long) sdram_addr2);
 168                udelay(100);
 169        }
 170
 171        /*
 172         * Issue 8 MODE-set command.
 173         */
 174        out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
 175        asm("sync;msync");
 176        *sdram_addr = 0xff;
 177        ppcDcbf((unsigned long) sdram_addr);
 178        *sdram_addr2 = 0xff;
 179        ppcDcbf((unsigned long) sdram_addr2);
 180        udelay(100);
 181
 182        /*
 183         * Issue RFEN command.
 184         */
 185        out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
 186        asm("sync;msync");
 187        *sdram_addr = 0xff;
 188        ppcDcbf((unsigned long) sdram_addr);
 189        *sdram_addr2 = 0xff;
 190        ppcDcbf((unsigned long) sdram_addr2);
 191        udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 192
 193#endif  /* enable SDRAM init */
 194}
 195
 196#if defined(CONFIG_SYS_DRAM_TEST)
 197int
 198testdram(void)
 199{
 200        uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
 201        uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 202        uint *p;
 203
 204        printf("Testing DRAM from 0x%08x to 0x%08x\n",
 205               CONFIG_SYS_MEMTEST_START,
 206               CONFIG_SYS_MEMTEST_END);
 207
 208        printf("DRAM test phase 1:\n");
 209        for (p = pstart; p < pend; p++)
 210                *p = 0xaaaaaaaa;
 211
 212        for (p = pstart; p < pend; p++) {
 213                if (*p != 0xaaaaaaaa) {
 214                        printf ("DRAM test fails at: %08x\n", (uint) p);
 215                        return 1;
 216                }
 217        }
 218
 219        printf("DRAM test phase 2:\n");
 220        for (p = pstart; p < pend; p++)
 221                *p = 0x55555555;
 222
 223        for (p = pstart; p < pend; p++) {
 224                if (*p != 0x55555555) {
 225                        printf ("DRAM test fails at: %08x\n", (uint) p);
 226                        return 1;
 227                }
 228        }
 229
 230        printf("DRAM test passed.\n");
 231        return 0;
 232}
 233#endif
 234
 235#ifdef CONFIG_PCI1
 236static struct pci_controller pci1_hose;
 237#endif  /* CONFIG_PCI1 */
 238
 239#ifdef CONFIG_PCI
 240void
 241pci_init_board(void)
 242{
 243        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 244        int first_free_busno = 0;
 245
 246#ifdef CONFIG_PCI1
 247        struct fsl_pci_info pci_info;
 248        u32 devdisr = in_be32(&gur->devdisr);
 249        u32 pordevsr = in_be32(&gur->pordevsr);
 250        u32 porpllsr = in_be32(&gur->porpllsr);
 251
 252        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 253                uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
 254                uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 255                uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 256                uint pci_speed = CONFIG_SYS_CLK_FREQ;   /* get_clock_freq() */
 257
 258                printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
 259                        (pci_32) ? 32 : 64,
 260                        (pci_speed == 33000000) ? "33" :
 261                        (pci_speed == 66000000) ? "66" : "unknown",
 262                        pci_clk_sel ? "sync" : "async",
 263                        pci_arb ? "arbiter" : "external-arbiter");
 264
 265                SET_STD_PCI_INFO(pci_info, 1);
 266                set_next_law(pci_info.mem_phys,
 267                        law_size_bits(pci_info.mem_size), pci_info.law);
 268                set_next_law(pci_info.io_phys,
 269                        law_size_bits(pci_info.io_size), pci_info.law);
 270
 271                first_free_busno = fsl_pci_init_port(&pci_info,
 272                                        &pci1_hose, first_free_busno);
 273        } else {
 274                printf("PCI: disabled\n");
 275        }
 276
 277        puts("\n");
 278#else
 279        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 280#endif
 281
 282        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
 283
 284        fsl_pcie_init_board(first_free_busno);
 285}
 286#endif
 287
 288int board_eth_init(bd_t *bis)
 289{
 290        tsec_standard_init(bis);
 291        pci_eth_init(bis);
 292        return 0;       /* otherwise cpu_eth_init gets run */
 293}
 294
 295int last_stage_init(void)
 296{
 297        return 0;
 298}
 299
 300#if defined(CONFIG_OF_BOARD_SETUP)
 301int ft_board_setup(void *blob, bd_t *bd)
 302{
 303        ft_cpu_setup(blob, bd);
 304
 305#ifdef CONFIG_FSL_PCI_INIT
 306        FT_FSL_PCI_SETUP;
 307#endif
 308
 309        return 0;
 310}
 311#endif
 312