1
2
3
4
5
6#include <common.h>
7#include <clk-uclass.h>
8#include <div64.h>
9#include <dm.h>
10#include <regmap.h>
11#include <spl.h>
12#include <syscon.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <dt-bindings/clock/stm32mp1-clks.h>
16#include <dt-bindings/clock/stm32mp1-clksrc.h>
17
18#ifndef CONFIG_STM32MP1_TRUSTED
19#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
20
21#define STM32MP1_CLOCK_TREE_INIT
22#endif
23#endif
24
25#define MAX_HSI_HZ 64000000
26
27
28#define TIMEOUT_200MS 200000
29#define TIMEOUT_1S 1000000
30
31
32#define STGENC_CNTCR 0x00
33#define STGENC_CNTSR 0x04
34#define STGENC_CNTCVL 0x08
35#define STGENC_CNTCVU 0x0C
36#define STGENC_CNTFID0 0x20
37
38#define STGENC_CNTCR_EN BIT(0)
39
40
41#define RCC_OCENSETR 0x0C
42#define RCC_OCENCLRR 0x10
43#define RCC_HSICFGR 0x18
44#define RCC_MPCKSELR 0x20
45#define RCC_ASSCKSELR 0x24
46#define RCC_RCK12SELR 0x28
47#define RCC_MPCKDIVR 0x2C
48#define RCC_AXIDIVR 0x30
49#define RCC_APB4DIVR 0x3C
50#define RCC_APB5DIVR 0x40
51#define RCC_RTCDIVR 0x44
52#define RCC_MSSCKSELR 0x48
53#define RCC_PLL1CR 0x80
54#define RCC_PLL1CFGR1 0x84
55#define RCC_PLL1CFGR2 0x88
56#define RCC_PLL1FRACR 0x8C
57#define RCC_PLL1CSGR 0x90
58#define RCC_PLL2CR 0x94
59#define RCC_PLL2CFGR1 0x98
60#define RCC_PLL2CFGR2 0x9C
61#define RCC_PLL2FRACR 0xA0
62#define RCC_PLL2CSGR 0xA4
63#define RCC_I2C46CKSELR 0xC0
64#define RCC_CPERCKSELR 0xD0
65#define RCC_STGENCKSELR 0xD4
66#define RCC_DDRITFCR 0xD8
67#define RCC_BDCR 0x140
68#define RCC_RDLSICR 0x144
69#define RCC_MP_APB4ENSETR 0x200
70#define RCC_MP_APB5ENSETR 0x208
71#define RCC_MP_AHB5ENSETR 0x210
72#define RCC_MP_AHB6ENSETR 0x218
73#define RCC_OCRDYR 0x808
74#define RCC_DBGCFGR 0x80C
75#define RCC_RCK3SELR 0x820
76#define RCC_RCK4SELR 0x824
77#define RCC_MCUDIVR 0x830
78#define RCC_APB1DIVR 0x834
79#define RCC_APB2DIVR 0x838
80#define RCC_APB3DIVR 0x83C
81#define RCC_PLL3CR 0x880
82#define RCC_PLL3CFGR1 0x884
83#define RCC_PLL3CFGR2 0x888
84#define RCC_PLL3FRACR 0x88C
85#define RCC_PLL3CSGR 0x890
86#define RCC_PLL4CR 0x894
87#define RCC_PLL4CFGR1 0x898
88#define RCC_PLL4CFGR2 0x89C
89#define RCC_PLL4FRACR 0x8A0
90#define RCC_PLL4CSGR 0x8A4
91#define RCC_I2C12CKSELR 0x8C0
92#define RCC_I2C35CKSELR 0x8C4
93#define RCC_SPI2S1CKSELR 0x8D8
94#define RCC_UART6CKSELR 0x8E4
95#define RCC_UART24CKSELR 0x8E8
96#define RCC_UART35CKSELR 0x8EC
97#define RCC_UART78CKSELR 0x8F0
98#define RCC_SDMMC12CKSELR 0x8F4
99#define RCC_SDMMC3CKSELR 0x8F8
100#define RCC_ETHCKSELR 0x8FC
101#define RCC_QSPICKSELR 0x900
102#define RCC_FMCCKSELR 0x904
103#define RCC_USBCKSELR 0x91C
104#define RCC_DSICKSELR 0x924
105#define RCC_ADCCKSELR 0x928
106#define RCC_MP_APB1ENSETR 0xA00
107#define RCC_MP_APB2ENSETR 0XA08
108#define RCC_MP_APB3ENSETR 0xA10
109#define RCC_MP_AHB2ENSETR 0xA18
110#define RCC_MP_AHB3ENSETR 0xA20
111#define RCC_MP_AHB4ENSETR 0xA28
112
113
114#define RCC_SELR_SRC_MASK GENMASK(2, 0)
115#define RCC_SELR_SRCRDY BIT(31)
116
117
118#define RCC_MPCKSELR_HSI 0
119#define RCC_MPCKSELR_HSE 1
120#define RCC_MPCKSELR_PLL 2
121#define RCC_MPCKSELR_PLL_MPUDIV 3
122
123
124#define RCC_ASSCKSELR_HSI 0
125#define RCC_ASSCKSELR_HSE 1
126#define RCC_ASSCKSELR_PLL 2
127
128
129#define RCC_MSSCKSELR_HSI 0
130#define RCC_MSSCKSELR_HSE 1
131#define RCC_MSSCKSELR_CSI 2
132#define RCC_MSSCKSELR_PLL 3
133
134
135#define RCC_CPERCKSELR_HSI 0
136#define RCC_CPERCKSELR_CSI 1
137#define RCC_CPERCKSELR_HSE 2
138
139
140#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
141#define RCC_DIVR_DIVRDY BIT(31)
142
143
144#define RCC_APBXDIV_MASK GENMASK(2, 0)
145#define RCC_MPUDIV_MASK GENMASK(2, 0)
146#define RCC_AXIDIV_MASK GENMASK(2, 0)
147#define RCC_MCUDIV_MASK GENMASK(3, 0)
148
149
150#define RCC_MP_ENCLRR_OFFSET 4
151
152
153#define RCC_BDCR_LSEON BIT(0)
154#define RCC_BDCR_LSEBYP BIT(1)
155#define RCC_BDCR_LSERDY BIT(2)
156#define RCC_BDCR_DIGBYP BIT(3)
157#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
158#define RCC_BDCR_LSEDRV_SHIFT 4
159#define RCC_BDCR_LSECSSON BIT(8)
160#define RCC_BDCR_RTCCKEN BIT(20)
161#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
162#define RCC_BDCR_RTCSRC_SHIFT 16
163
164
165#define RCC_RDLSICR_LSION BIT(0)
166#define RCC_RDLSICR_LSIRDY BIT(1)
167
168
169#define RCC_PLLNCR_PLLON BIT(0)
170#define RCC_PLLNCR_PLLRDY BIT(1)
171#define RCC_PLLNCR_SSCG_CTRL BIT(2)
172#define RCC_PLLNCR_DIVPEN BIT(4)
173#define RCC_PLLNCR_DIVQEN BIT(5)
174#define RCC_PLLNCR_DIVREN BIT(6)
175#define RCC_PLLNCR_DIVEN_SHIFT 4
176
177
178#define RCC_PLLNCFGR1_DIVM_SHIFT 16
179#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
180#define RCC_PLLNCFGR1_DIVN_SHIFT 0
181#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
182
183#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
184#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
185
186
187#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
188#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
189#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
190#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
191#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
192#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
193#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
194#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
195
196
197#define RCC_PLLNFRACR_FRACV_SHIFT 3
198#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
199#define RCC_PLLNFRACR_FRACLE BIT(16)
200
201
202#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
203#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
204#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
205#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
206#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
207#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
208
209
210#define RCC_OCENR_HSION BIT(0)
211#define RCC_OCENR_CSION BIT(4)
212#define RCC_OCENR_DIGBYP BIT(7)
213#define RCC_OCENR_HSEON BIT(8)
214#define RCC_OCENR_HSEBYP BIT(10)
215#define RCC_OCENR_HSECSSON BIT(11)
216
217
218#define RCC_OCRDYR_HSIRDY BIT(0)
219#define RCC_OCRDYR_HSIDIVRDY BIT(2)
220#define RCC_OCRDYR_CSIRDY BIT(4)
221#define RCC_OCRDYR_HSERDY BIT(8)
222
223
224#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
225#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
226#define RCC_DDRITFCR_DDRCKMOD_SSR 0
227
228
229#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
230
231
232#define RCC_MCOCFG_MCOON BIT(12)
233#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
234#define RCC_MCOCFG_MCODIV_SHIFT 4
235#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
236
237enum stm32mp1_parent_id {
238
239
240
241
242 _HSI,
243 _HSE,
244 _CSI,
245 _LSI,
246 _LSE,
247 _I2S_CKIN,
248 NB_OSC,
249
250
251 _HSI_KER = NB_OSC,
252 _HSE_KER,
253 _HSE_KER_DIV2,
254 _CSI_KER,
255 _PLL1_P,
256 _PLL1_Q,
257 _PLL1_R,
258 _PLL2_P,
259 _PLL2_Q,
260 _PLL2_R,
261 _PLL3_P,
262 _PLL3_Q,
263 _PLL3_R,
264 _PLL4_P,
265 _PLL4_Q,
266 _PLL4_R,
267 _ACLK,
268 _PCLK1,
269 _PCLK2,
270 _PCLK3,
271 _PCLK4,
272 _PCLK5,
273 _HCLK6,
274 _HCLK2,
275 _CK_PER,
276 _CK_MPU,
277 _CK_MCU,
278 _DSI_PHY,
279 _USB_PHY_48,
280 _PARENT_NB,
281 _UNKNOWN_ID = 0xff,
282};
283
284enum stm32mp1_parent_sel {
285 _I2C12_SEL,
286 _I2C35_SEL,
287 _I2C46_SEL,
288 _UART6_SEL,
289 _UART24_SEL,
290 _UART35_SEL,
291 _UART78_SEL,
292 _SDMMC12_SEL,
293 _SDMMC3_SEL,
294 _ETH_SEL,
295 _QSPI_SEL,
296 _FMC_SEL,
297 _USBPHY_SEL,
298 _USBO_SEL,
299 _STGEN_SEL,
300 _DSI_SEL,
301 _ADC12_SEL,
302 _SPI1_SEL,
303 _PARENT_SEL_NB,
304 _UNKNOWN_SEL = 0xff,
305};
306
307enum stm32mp1_pll_id {
308 _PLL1,
309 _PLL2,
310 _PLL3,
311 _PLL4,
312 _PLL_NB
313};
314
315enum stm32mp1_div_id {
316 _DIV_P,
317 _DIV_Q,
318 _DIV_R,
319 _DIV_NB,
320};
321
322enum stm32mp1_clksrc_id {
323 CLKSRC_MPU,
324 CLKSRC_AXI,
325 CLKSRC_MCU,
326 CLKSRC_PLL12,
327 CLKSRC_PLL3,
328 CLKSRC_PLL4,
329 CLKSRC_RTC,
330 CLKSRC_MCO1,
331 CLKSRC_MCO2,
332 CLKSRC_NB
333};
334
335enum stm32mp1_clkdiv_id {
336 CLKDIV_MPU,
337 CLKDIV_AXI,
338 CLKDIV_MCU,
339 CLKDIV_APB1,
340 CLKDIV_APB2,
341 CLKDIV_APB3,
342 CLKDIV_APB4,
343 CLKDIV_APB5,
344 CLKDIV_RTC,
345 CLKDIV_MCO1,
346 CLKDIV_MCO2,
347 CLKDIV_NB
348};
349
350enum stm32mp1_pllcfg {
351 PLLCFG_M,
352 PLLCFG_N,
353 PLLCFG_P,
354 PLLCFG_Q,
355 PLLCFG_R,
356 PLLCFG_O,
357 PLLCFG_NB
358};
359
360enum stm32mp1_pllcsg {
361 PLLCSG_MOD_PER,
362 PLLCSG_INC_STEP,
363 PLLCSG_SSCG_MODE,
364 PLLCSG_NB
365};
366
367enum stm32mp1_plltype {
368 PLL_800,
369 PLL_1600,
370 PLL_TYPE_NB
371};
372
373struct stm32mp1_pll {
374 u8 refclk_min;
375 u8 refclk_max;
376 u8 divn_max;
377};
378
379struct stm32mp1_clk_gate {
380 u16 offset;
381 u8 bit;
382 u8 index;
383 u8 set_clr;
384 u8 sel;
385 u8 fixed;
386};
387
388struct stm32mp1_clk_sel {
389 u16 offset;
390 u8 src;
391 u8 msk;
392 u8 nb_parent;
393 const u8 *parent;
394};
395
396#define REFCLK_SIZE 4
397struct stm32mp1_clk_pll {
398 enum stm32mp1_plltype plltype;
399 u16 rckxselr;
400 u16 pllxcfgr1;
401 u16 pllxcfgr2;
402 u16 pllxfracr;
403 u16 pllxcr;
404 u16 pllxcsgr;
405 u8 refclk[REFCLK_SIZE];
406};
407
408struct stm32mp1_clk_data {
409 const struct stm32mp1_clk_gate *gate;
410 const struct stm32mp1_clk_sel *sel;
411 const struct stm32mp1_clk_pll *pll;
412 const int nb_gate;
413};
414
415struct stm32mp1_clk_priv {
416 fdt_addr_t base;
417 const struct stm32mp1_clk_data *data;
418 ulong osc[NB_OSC];
419 struct udevice *osc_dev[NB_OSC];
420};
421
422#define STM32MP1_CLK(off, b, idx, s) \
423 { \
424 .offset = (off), \
425 .bit = (b), \
426 .index = (idx), \
427 .set_clr = 0, \
428 .sel = (s), \
429 .fixed = _UNKNOWN_ID, \
430 }
431
432#define STM32MP1_CLK_F(off, b, idx, f) \
433 { \
434 .offset = (off), \
435 .bit = (b), \
436 .index = (idx), \
437 .set_clr = 0, \
438 .sel = _UNKNOWN_SEL, \
439 .fixed = (f), \
440 }
441
442#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
443 { \
444 .offset = (off), \
445 .bit = (b), \
446 .index = (idx), \
447 .set_clr = 1, \
448 .sel = (s), \
449 .fixed = _UNKNOWN_ID, \
450 }
451
452#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
453 { \
454 .offset = (off), \
455 .bit = (b), \
456 .index = (idx), \
457 .set_clr = 1, \
458 .sel = _UNKNOWN_SEL, \
459 .fixed = (f), \
460 }
461
462#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
463 [(idx)] = { \
464 .offset = (off), \
465 .src = (s), \
466 .msk = (m), \
467 .parent = (p), \
468 .nb_parent = ARRAY_SIZE((p)) \
469 }
470
471#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
472 p1, p2, p3, p4) \
473 [(idx)] = { \
474 .plltype = (type), \
475 .rckxselr = (off1), \
476 .pllxcfgr1 = (off2), \
477 .pllxcfgr2 = (off3), \
478 .pllxfracr = (off4), \
479 .pllxcr = (off5), \
480 .pllxcsgr = (off6), \
481 .refclk[0] = (p1), \
482 .refclk[1] = (p2), \
483 .refclk[2] = (p3), \
484 .refclk[3] = (p4), \
485 }
486
487static const u8 stm32mp1_clks[][2] = {
488 {CK_PER, _CK_PER},
489 {CK_MPU, _CK_MPU},
490 {CK_AXI, _ACLK},
491 {CK_MCU, _CK_MCU},
492 {CK_HSE, _HSE},
493 {CK_CSI, _CSI},
494 {CK_LSI, _LSI},
495 {CK_LSE, _LSE},
496 {CK_HSI, _HSI},
497 {CK_HSE_DIV2, _HSE_KER_DIV2},
498};
499
500static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
501 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
502 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
503 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
504 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
505 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
506 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
507 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
508 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
509 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
510 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
511 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
512
513 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
514 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
515 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
516 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
517 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
518 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
519 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
520 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
521 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
522 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
523
524 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
525 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
526
527 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
528
529 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
530 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
531 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
532 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
533 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
534 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
535
536 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
537 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
538
539 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
540 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
541 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
542 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
543
544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
545 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
546
547 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
548 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
549 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
550 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
551 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
552 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
553 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
554 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
555 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
556 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
557 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
558
559 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
560
561 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
562 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
563 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
564 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
565 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
566 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
567 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
568 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
569 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
570
571 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
572};
573
574static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
575static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
576static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
577static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
578 _HSE_KER};
579static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
580 _HSE_KER};
581static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
582 _HSE_KER};
583static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
584 _HSE_KER};
585static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
586static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
587static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
588static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
589static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
590static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
591static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
592static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
593static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
594static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
595static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
596 _PLL3_R};
597
598static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
599 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
600 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
601 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
602 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
603 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
604 uart24_parents),
605 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
606 uart35_parents),
607 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
608 uart78_parents),
609 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
610 sdmmc12_parents),
611 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
612 sdmmc3_parents),
613 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
614 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
615 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
616 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
617 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
618 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
619 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
620 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
621 STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
622};
623
624#ifdef STM32MP1_CLOCK_TREE_INIT
625
626#define DIVN_MIN 24
627static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
628 [PLL_800] = {
629 .refclk_min = 4,
630 .refclk_max = 16,
631 .divn_max = 99,
632 },
633 [PLL_1600] = {
634 .refclk_min = 8,
635 .refclk_max = 16,
636 .divn_max = 199,
637 },
638};
639#endif
640
641static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
642 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
643 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
644 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
645 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
646 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
647 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
648 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
649 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
650 STM32MP1_CLK_PLL(_PLL3, PLL_800,
651 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
652 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
653 _HSI, _HSE, _CSI, _UNKNOWN_ID),
654 STM32MP1_CLK_PLL(_PLL4, PLL_800,
655 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
656 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
657 _HSI, _HSE, _CSI, _I2S_CKIN),
658};
659
660
661
662static const u8 stm32mp1_mcu_div[16] = {
663 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
664};
665
666
667#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
668#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
669static const u8 stm32mp1_mpu_apbx_div[8] = {
670 0, 1, 2, 3, 4, 4, 4, 4
671};
672
673
674static const u8 stm32mp1_axi_div[8] = {
675 1, 2, 3, 4, 4, 4, 4, 4
676};
677
678static const __maybe_unused
679char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
680 [_HSI] = "HSI",
681 [_HSE] = "HSE",
682 [_CSI] = "CSI",
683 [_LSI] = "LSI",
684 [_LSE] = "LSE",
685 [_I2S_CKIN] = "I2S_CKIN",
686 [_HSI_KER] = "HSI_KER",
687 [_HSE_KER] = "HSE_KER",
688 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
689 [_CSI_KER] = "CSI_KER",
690 [_PLL1_P] = "PLL1_P",
691 [_PLL1_Q] = "PLL1_Q",
692 [_PLL1_R] = "PLL1_R",
693 [_PLL2_P] = "PLL2_P",
694 [_PLL2_Q] = "PLL2_Q",
695 [_PLL2_R] = "PLL2_R",
696 [_PLL3_P] = "PLL3_P",
697 [_PLL3_Q] = "PLL3_Q",
698 [_PLL3_R] = "PLL3_R",
699 [_PLL4_P] = "PLL4_P",
700 [_PLL4_Q] = "PLL4_Q",
701 [_PLL4_R] = "PLL4_R",
702 [_ACLK] = "ACLK",
703 [_PCLK1] = "PCLK1",
704 [_PCLK2] = "PCLK2",
705 [_PCLK3] = "PCLK3",
706 [_PCLK4] = "PCLK4",
707 [_PCLK5] = "PCLK5",
708 [_HCLK6] = "KCLK6",
709 [_HCLK2] = "HCLK2",
710 [_CK_PER] = "CK_PER",
711 [_CK_MPU] = "CK_MPU",
712 [_CK_MCU] = "CK_MCU",
713 [_USB_PHY_48] = "USB_PHY_48",
714 [_DSI_PHY] = "DSI_PHY_PLL",
715};
716
717static const __maybe_unused
718char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
719 [_I2C12_SEL] = "I2C12",
720 [_I2C35_SEL] = "I2C35",
721 [_I2C46_SEL] = "I2C46",
722 [_UART6_SEL] = "UART6",
723 [_UART24_SEL] = "UART24",
724 [_UART35_SEL] = "UART35",
725 [_UART78_SEL] = "UART78",
726 [_SDMMC12_SEL] = "SDMMC12",
727 [_SDMMC3_SEL] = "SDMMC3",
728 [_ETH_SEL] = "ETH",
729 [_QSPI_SEL] = "QSPI",
730 [_FMC_SEL] = "FMC",
731 [_USBPHY_SEL] = "USBPHY",
732 [_USBO_SEL] = "USBO",
733 [_STGEN_SEL] = "STGEN",
734 [_DSI_SEL] = "DSI",
735 [_ADC12_SEL] = "ADC12",
736 [_SPI1_SEL] = "SPI1",
737};
738
739static const struct stm32mp1_clk_data stm32mp1_data = {
740 .gate = stm32mp1_clk_gate,
741 .sel = stm32mp1_clk_sel,
742 .pll = stm32mp1_clk_pll,
743 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
744};
745
746static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
747{
748 if (idx >= NB_OSC) {
749 debug("%s: clk id %d not found\n", __func__, idx);
750 return 0;
751 }
752
753 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
754 (u32)priv->osc[idx], priv->osc[idx] / 1000);
755
756 return priv->osc[idx];
757}
758
759static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
760{
761 const struct stm32mp1_clk_gate *gate = priv->data->gate;
762 int i, nb_clks = priv->data->nb_gate;
763
764 for (i = 0; i < nb_clks; i++) {
765 if (gate[i].index == id)
766 break;
767 }
768
769 if (i == nb_clks) {
770 printf("%s: clk id %d not found\n", __func__, (u32)id);
771 return -EINVAL;
772 }
773
774 return i;
775}
776
777static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
778 int i)
779{
780 const struct stm32mp1_clk_gate *gate = priv->data->gate;
781
782 if (gate[i].sel > _PARENT_SEL_NB) {
783 printf("%s: parents for clk id %d not found\n",
784 __func__, i);
785 return -EINVAL;
786 }
787
788 return gate[i].sel;
789}
790
791static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
792 int i)
793{
794 const struct stm32mp1_clk_gate *gate = priv->data->gate;
795
796 if (gate[i].fixed == _UNKNOWN_ID)
797 return -ENOENT;
798
799 return gate[i].fixed;
800}
801
802static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
803 unsigned long id)
804{
805 const struct stm32mp1_clk_sel *sel = priv->data->sel;
806 int i;
807 int s, p;
808
809 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
810 if (stm32mp1_clks[i][0] == id)
811 return stm32mp1_clks[i][1];
812
813 i = stm32mp1_clk_get_id(priv, id);
814 if (i < 0)
815 return i;
816
817 p = stm32mp1_clk_get_fixed_parent(priv, i);
818 if (p >= 0 && p < _PARENT_NB)
819 return p;
820
821 s = stm32mp1_clk_get_sel(priv, i);
822 if (s < 0)
823 return s;
824
825 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
826
827 if (p < sel[s].nb_parent) {
828#ifdef DEBUG
829 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
830 stm32mp1_clk_parent_name[sel[s].parent[p]],
831 stm32mp1_clk_parent_sel_name[s],
832 (u32)id);
833#endif
834 return sel[s].parent[p];
835 }
836
837 pr_err("%s: no parents defined for clk id %d\n",
838 __func__, (u32)id);
839
840 return -EINVAL;
841}
842
843static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
844 int pll_id)
845{
846 const struct stm32mp1_clk_pll *pll = priv->data->pll;
847 u32 selr;
848 int src;
849 ulong refclk;
850
851
852 selr = readl(priv->base + pll[pll_id].rckxselr);
853 src = selr & RCC_SELR_SRC_MASK;
854
855 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
856 debug("PLL%d : selr=%x refclk = %d kHz\n",
857 pll_id, selr, (u32)(refclk / 1000));
858
859 return refclk;
860}
861
862
863
864
865
866
867
868static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
869 int pll_id)
870{
871 const struct stm32mp1_clk_pll *pll = priv->data->pll;
872 int divm, divn;
873 ulong refclk, fvco;
874 u32 cfgr1, fracr;
875
876 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
877 fracr = readl(priv->base + pll[pll_id].pllxfracr);
878
879 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
880 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
881
882 debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
883 pll_id, cfgr1, fracr, divn, divm);
884
885 refclk = pll_get_fref_ck(priv, pll_id);
886
887
888
889
890
891
892 if (fracr & RCC_PLLNFRACR_FRACLE) {
893 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
894 >> RCC_PLLNFRACR_FRACV_SHIFT;
895 fvco = (ulong)lldiv((unsigned long long)refclk *
896 (((divn + 1) << 13) + fracv),
897 ((unsigned long long)(divm + 1)) << 13);
898 } else {
899 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
900 }
901 debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
902
903 return fvco;
904}
905
906static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
907 int pll_id, int div_id)
908{
909 const struct stm32mp1_clk_pll *pll = priv->data->pll;
910 int divy;
911 ulong dfout;
912 u32 cfgr2;
913
914 debug("%s(%d, %d)\n", __func__, pll_id, div_id);
915 if (div_id >= _DIV_NB)
916 return 0;
917
918 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
919 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
920
921 debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
922
923 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
924 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
925
926 return dfout;
927}
928
929static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
930{
931 u32 reg;
932 ulong clock = 0;
933
934 switch (p) {
935 case _CK_MPU:
936
937 reg = readl(priv->base + RCC_MPCKSELR);
938 switch (reg & RCC_SELR_SRC_MASK) {
939 case RCC_MPCKSELR_HSI:
940 clock = stm32mp1_clk_get_fixed(priv, _HSI);
941 break;
942 case RCC_MPCKSELR_HSE:
943 clock = stm32mp1_clk_get_fixed(priv, _HSE);
944 break;
945 case RCC_MPCKSELR_PLL:
946 case RCC_MPCKSELR_PLL_MPUDIV:
947 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
948 if (p == RCC_MPCKSELR_PLL_MPUDIV) {
949 reg = readl(priv->base + RCC_MPCKDIVR);
950 clock /= stm32mp1_mpu_div[reg &
951 RCC_MPUDIV_MASK];
952 }
953 break;
954 }
955 break;
956
957 case _ACLK:
958 case _HCLK2:
959 case _HCLK6:
960 case _PCLK4:
961 case _PCLK5:
962 reg = readl(priv->base + RCC_ASSCKSELR);
963 switch (reg & RCC_SELR_SRC_MASK) {
964 case RCC_ASSCKSELR_HSI:
965 clock = stm32mp1_clk_get_fixed(priv, _HSI);
966 break;
967 case RCC_ASSCKSELR_HSE:
968 clock = stm32mp1_clk_get_fixed(priv, _HSE);
969 break;
970 case RCC_ASSCKSELR_PLL:
971 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
972 break;
973 }
974
975
976 reg = readl(priv->base + RCC_AXIDIVR);
977 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
978
979 switch (p) {
980 case _PCLK4:
981 reg = readl(priv->base + RCC_APB4DIVR);
982 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
983 break;
984 case _PCLK5:
985 reg = readl(priv->base + RCC_APB5DIVR);
986 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
987 break;
988 default:
989 break;
990 }
991 break;
992
993 case _CK_MCU:
994 case _PCLK1:
995 case _PCLK2:
996 case _PCLK3:
997 reg = readl(priv->base + RCC_MSSCKSELR);
998 switch (reg & RCC_SELR_SRC_MASK) {
999 case RCC_MSSCKSELR_HSI:
1000 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1001 break;
1002 case RCC_MSSCKSELR_HSE:
1003 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1004 break;
1005 case RCC_MSSCKSELR_CSI:
1006 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1007 break;
1008 case RCC_MSSCKSELR_PLL:
1009 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1010 break;
1011 }
1012
1013
1014 reg = readl(priv->base + RCC_MCUDIVR);
1015 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1016
1017 switch (p) {
1018 case _PCLK1:
1019 reg = readl(priv->base + RCC_APB1DIVR);
1020 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1021 break;
1022 case _PCLK2:
1023 reg = readl(priv->base + RCC_APB2DIVR);
1024 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1025 break;
1026 case _PCLK3:
1027 reg = readl(priv->base + RCC_APB3DIVR);
1028 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1029 break;
1030 case _CK_MCU:
1031 default:
1032 break;
1033 }
1034 break;
1035 case _CK_PER:
1036 reg = readl(priv->base + RCC_CPERCKSELR);
1037 switch (reg & RCC_SELR_SRC_MASK) {
1038 case RCC_CPERCKSELR_HSI:
1039 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1040 break;
1041 case RCC_CPERCKSELR_HSE:
1042 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1043 break;
1044 case RCC_CPERCKSELR_CSI:
1045 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1046 break;
1047 }
1048 break;
1049 case _HSI:
1050 case _HSI_KER:
1051 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1052 break;
1053 case _CSI:
1054 case _CSI_KER:
1055 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1056 break;
1057 case _HSE:
1058 case _HSE_KER:
1059 case _HSE_KER_DIV2:
1060 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1061 if (p == _HSE_KER_DIV2)
1062 clock >>= 1;
1063 break;
1064 case _LSI:
1065 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1066 break;
1067 case _LSE:
1068 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1069 break;
1070
1071 case _PLL1_P:
1072 case _PLL1_Q:
1073 case _PLL1_R:
1074 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1075 break;
1076 case _PLL2_P:
1077 case _PLL2_Q:
1078 case _PLL2_R:
1079 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1080 break;
1081 case _PLL3_P:
1082 case _PLL3_Q:
1083 case _PLL3_R:
1084 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1085 break;
1086 case _PLL4_P:
1087 case _PLL4_Q:
1088 case _PLL4_R:
1089 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1090 break;
1091
1092 case _USB_PHY_48:
1093 clock = 48000000;
1094 break;
1095 case _DSI_PHY:
1096 {
1097 struct clk clk;
1098 struct udevice *dev = NULL;
1099
1100 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1101 &dev)) {
1102 if (clk_request(dev, &clk)) {
1103 pr_err("ck_dsi_phy request");
1104 } else {
1105 clk.id = 0;
1106 clock = clk_get_rate(&clk);
1107 }
1108 }
1109 break;
1110 }
1111 default:
1112 break;
1113 }
1114
1115 debug("%s(%d) clock = %lx : %ld kHz\n",
1116 __func__, p, clock, clock / 1000);
1117
1118 return clock;
1119}
1120
1121static int stm32mp1_clk_enable(struct clk *clk)
1122{
1123 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1124 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1125 int i = stm32mp1_clk_get_id(priv, clk->id);
1126
1127 if (i < 0)
1128 return i;
1129
1130 if (gate[i].set_clr)
1131 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1132 else
1133 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1134
1135 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1136
1137 return 0;
1138}
1139
1140static int stm32mp1_clk_disable(struct clk *clk)
1141{
1142 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1143 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1144 int i = stm32mp1_clk_get_id(priv, clk->id);
1145
1146 if (i < 0)
1147 return i;
1148
1149 if (gate[i].set_clr)
1150 writel(BIT(gate[i].bit),
1151 priv->base + gate[i].offset
1152 + RCC_MP_ENCLRR_OFFSET);
1153 else
1154 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1155
1156 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1157
1158 return 0;
1159}
1160
1161static ulong stm32mp1_clk_get_rate(struct clk *clk)
1162{
1163 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1164 int p = stm32mp1_clk_get_parent(priv, clk->id);
1165 ulong rate;
1166
1167 if (p < 0)
1168 return 0;
1169
1170 rate = stm32mp1_clk_get(priv, p);
1171
1172#ifdef DEBUG
1173 debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1174 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1175#endif
1176 return rate;
1177}
1178
1179#ifdef STM32MP1_CLOCK_TREE_INIT
1180static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1181 u32 mask_on)
1182{
1183 u32 address = rcc + offset;
1184
1185 if (enable)
1186 setbits_le32(address, mask_on);
1187 else
1188 clrbits_le32(address, mask_on);
1189}
1190
1191static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1192{
1193 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1194}
1195
1196static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1197 u32 mask_rdy)
1198{
1199 u32 mask_test = 0;
1200 u32 address = rcc + offset;
1201 u32 val;
1202 int ret;
1203
1204 if (enable)
1205 mask_test = mask_rdy;
1206
1207 ret = readl_poll_timeout(address, val,
1208 (val & mask_rdy) == mask_test,
1209 TIMEOUT_1S);
1210
1211 if (ret)
1212 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1213 mask_rdy, address, enable, readl(address));
1214
1215 return ret;
1216}
1217
1218static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1219 int lsedrv)
1220{
1221 u32 value;
1222
1223 if (digbyp)
1224 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1225
1226 if (bypass || digbyp)
1227 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1228
1229
1230
1231
1232
1233 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1234 >> RCC_BDCR_LSEDRV_SHIFT;
1235
1236 while (value != lsedrv) {
1237 if (value > lsedrv)
1238 value--;
1239 else
1240 value++;
1241
1242 clrsetbits_le32(rcc + RCC_BDCR,
1243 RCC_BDCR_LSEDRV_MASK,
1244 value << RCC_BDCR_LSEDRV_SHIFT);
1245 }
1246
1247 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1248}
1249
1250static void stm32mp1_lse_wait(fdt_addr_t rcc)
1251{
1252 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1253}
1254
1255static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1256{
1257 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1258 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1259}
1260
1261static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1262{
1263 if (digbyp)
1264 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1265 if (bypass || digbyp)
1266 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1267
1268 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1269 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1270
1271 if (css)
1272 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1273}
1274
1275static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1276{
1277 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1278 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1279}
1280
1281static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1282{
1283 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1284 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1285}
1286
1287static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1288{
1289 u32 address = rcc + RCC_OCRDYR;
1290 u32 val;
1291 int ret;
1292
1293 clrsetbits_le32(rcc + RCC_HSICFGR,
1294 RCC_HSICFGR_HSIDIV_MASK,
1295 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1296
1297 ret = readl_poll_timeout(address, val,
1298 val & RCC_OCRDYR_HSIDIVRDY,
1299 TIMEOUT_200MS);
1300 if (ret)
1301 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1302 address, readl(address));
1303
1304 return ret;
1305}
1306
1307static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1308{
1309 u8 hsidiv;
1310 u32 hsidivfreq = MAX_HSI_HZ;
1311
1312 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1313 hsidivfreq = hsidivfreq / 2)
1314 if (hsidivfreq == hsifreq)
1315 break;
1316
1317 if (hsidiv == 4) {
1318 pr_err("clk-hsi frequency invalid");
1319 return -1;
1320 }
1321
1322 if (hsidiv > 0)
1323 return stm32mp1_set_hsidiv(rcc, hsidiv);
1324
1325 return 0;
1326}
1327
1328static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1329{
1330 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1331
1332 clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1333 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1334 RCC_PLLNCR_DIVREN,
1335 RCC_PLLNCR_PLLON);
1336}
1337
1338static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1339{
1340 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1341 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1342 u32 val;
1343 int ret;
1344
1345 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1346 TIMEOUT_200MS);
1347
1348 if (ret) {
1349 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1350 pll_id, pllxcr, readl(pllxcr));
1351 return ret;
1352 }
1353
1354
1355 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1356
1357 return 0;
1358}
1359
1360static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1361{
1362 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1363 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1364 u32 val;
1365
1366
1367 clrbits_le32(pllxcr,
1368 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1369
1370
1371 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1372
1373
1374 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1375 TIMEOUT_200MS);
1376}
1377
1378static void pll_config_output(struct stm32mp1_clk_priv *priv,
1379 int pll_id, u32 *pllcfg)
1380{
1381 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1382 fdt_addr_t rcc = priv->base;
1383 u32 value;
1384
1385 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1386 & RCC_PLLNCFGR2_DIVP_MASK;
1387 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1388 & RCC_PLLNCFGR2_DIVQ_MASK;
1389 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1390 & RCC_PLLNCFGR2_DIVR_MASK;
1391 writel(value, rcc + pll[pll_id].pllxcfgr2);
1392}
1393
1394static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1395 u32 *pllcfg, u32 fracv)
1396{
1397 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1398 fdt_addr_t rcc = priv->base;
1399 enum stm32mp1_plltype type = pll[pll_id].plltype;
1400 int src;
1401 ulong refclk;
1402 u8 ifrge = 0;
1403 u32 value;
1404
1405 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1406
1407 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1408 (pllcfg[PLLCFG_M] + 1);
1409
1410 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1411 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1412 debug("invalid refclk = %x\n", (u32)refclk);
1413 return -EINVAL;
1414 }
1415 if (type == PLL_800 && refclk >= 8000000)
1416 ifrge = 1;
1417
1418 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1419 & RCC_PLLNCFGR1_DIVN_MASK;
1420 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1421 & RCC_PLLNCFGR1_DIVM_MASK;
1422 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1423 & RCC_PLLNCFGR1_IFRGE_MASK;
1424 writel(value, rcc + pll[pll_id].pllxcfgr1);
1425
1426
1427
1428
1429 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1430 rcc + pll[pll_id].pllxfracr);
1431
1432
1433 setbits_le32(rcc + pll[pll_id].pllxfracr,
1434 RCC_PLLNFRACR_FRACLE);
1435
1436 pll_config_output(priv, pll_id, pllcfg);
1437
1438 return 0;
1439}
1440
1441static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1442{
1443 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1444 u32 pllxcsg;
1445
1446 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1447 RCC_PLLNCSGR_MOD_PER_MASK) |
1448 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1449 RCC_PLLNCSGR_INC_STEP_MASK) |
1450 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1451 RCC_PLLNCSGR_SSCG_MODE_MASK);
1452
1453 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1454
1455 setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1456}
1457
1458static __maybe_unused int pll_set_rate(struct udevice *dev,
1459 int pll_id,
1460 int div_id,
1461 unsigned long clk_rate)
1462{
1463 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1464 unsigned int pllcfg[PLLCFG_NB];
1465 ofnode plloff;
1466 char name[12];
1467 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1468 enum stm32mp1_plltype type = pll[pll_id].plltype;
1469 int divm, divn, divy;
1470 int ret;
1471 ulong fck_ref;
1472 u32 fracv;
1473 u64 value;
1474
1475 if (div_id > _DIV_NB)
1476 return -EINVAL;
1477
1478 sprintf(name, "st,pll@%d", pll_id);
1479 plloff = dev_read_subnode(dev, name);
1480 if (!ofnode_valid(plloff))
1481 return -FDT_ERR_NOTFOUND;
1482
1483 ret = ofnode_read_u32_array(plloff, "cfg",
1484 pllcfg, PLLCFG_NB);
1485 if (ret < 0)
1486 return -FDT_ERR_NOTFOUND;
1487
1488 fck_ref = pll_get_fref_ck(priv, pll_id);
1489
1490 divm = pllcfg[PLLCFG_M];
1491
1492 divy = pllcfg[PLLCFG_P + div_id];
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502 value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1503 value = lldiv(value, fck_ref);
1504
1505 divn = (value >> 13) - 1;
1506 if (divn < DIVN_MIN ||
1507 divn > stm32mp1_pll[type].divn_max) {
1508 pr_err("divn invalid = %d", divn);
1509 return -EINVAL;
1510 }
1511 fracv = value - ((divn + 1) << 13);
1512 pllcfg[PLLCFG_N] = divn;
1513
1514
1515 pll_stop(priv, pll_id);
1516 pll_config(priv, pll_id, pllcfg, fracv);
1517 pll_start(priv, pll_id);
1518 pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1519
1520 return 0;
1521}
1522
1523static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1524{
1525 u32 address = priv->base + (clksrc >> 4);
1526 u32 val;
1527 int ret;
1528
1529 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1530 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1531 TIMEOUT_200MS);
1532 if (ret)
1533 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1534 clksrc, address, readl(address));
1535
1536 return ret;
1537}
1538
1539static void stgen_config(struct stm32mp1_clk_priv *priv)
1540{
1541 int p;
1542 u32 stgenc, cntfid0;
1543 ulong rate;
1544
1545 stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1546
1547 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1548 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1549 rate = stm32mp1_clk_get(priv, p);
1550
1551 if (cntfid0 != rate) {
1552 u64 counter;
1553
1554 pr_debug("System Generic Counter (STGEN) update\n");
1555 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1556 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1557 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1558 counter = lldiv(counter * (u64)rate, cntfid0);
1559 writel((u32)counter, stgenc + STGENC_CNTCVL);
1560 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1561 writel(rate, stgenc + STGENC_CNTFID0);
1562 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1563
1564 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1565
1566
1567 timer_init();
1568 pr_debug("gd->arch.timer_rate_hz = %x\n",
1569 (u32)gd->arch.timer_rate_hz);
1570 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1571 }
1572}
1573
1574static int set_clkdiv(unsigned int clkdiv, u32 address)
1575{
1576 u32 val;
1577 int ret;
1578
1579 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1580 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1581 TIMEOUT_200MS);
1582 if (ret)
1583 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1584 clkdiv, address, readl(address));
1585
1586 return ret;
1587}
1588
1589static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1590 u32 clksrc, u32 clkdiv)
1591{
1592 u32 address = priv->base + (clksrc >> 4);
1593
1594
1595
1596
1597
1598
1599 if (clksrc & 0x8) {
1600 clrbits_le32(address, RCC_MCOCFG_MCOON);
1601 } else {
1602 clrsetbits_le32(address,
1603 RCC_MCOCFG_MCOSRC_MASK,
1604 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1605 clrsetbits_le32(address,
1606 RCC_MCOCFG_MCODIV_MASK,
1607 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1608 setbits_le32(address, RCC_MCOCFG_MCOON);
1609 }
1610}
1611
1612static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1613 unsigned int clksrc,
1614 int lse_css)
1615{
1616 u32 address = priv->base + RCC_BDCR;
1617
1618 if (readl(address) & RCC_BDCR_RTCCKEN)
1619 goto skip_rtc;
1620
1621 if (clksrc == CLK_RTC_DISABLED)
1622 goto skip_rtc;
1623
1624 clrsetbits_le32(address,
1625 RCC_BDCR_RTCSRC_MASK,
1626 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1627
1628 setbits_le32(address, RCC_BDCR_RTCCKEN);
1629
1630skip_rtc:
1631 if (lse_css)
1632 setbits_le32(address, RCC_BDCR_LSECSSON);
1633}
1634
1635static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1636{
1637 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1638 u32 value = pkcs & 0xF;
1639 u32 mask = 0xF;
1640
1641 if (pkcs & BIT(31)) {
1642 mask <<= 4;
1643 value <<= 4;
1644 }
1645 clrsetbits_le32(address, mask, value);
1646}
1647
1648static int stm32mp1_clktree(struct udevice *dev)
1649{
1650 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1651 fdt_addr_t rcc = priv->base;
1652 unsigned int clksrc[CLKSRC_NB];
1653 unsigned int clkdiv[CLKDIV_NB];
1654 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1655 ofnode plloff[_PLL_NB];
1656 int ret;
1657 int i, len;
1658 int lse_css = 0;
1659 const u32 *pkcs_cell;
1660
1661
1662 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1663 if (ret < 0) {
1664 debug("field st,clksrc invalid: error %d\n", ret);
1665 return -FDT_ERR_NOTFOUND;
1666 }
1667
1668 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1669 if (ret < 0) {
1670 debug("field st,clkdiv invalid: error %d\n", ret);
1671 return -FDT_ERR_NOTFOUND;
1672 }
1673
1674
1675 for (i = 0; i < _PLL_NB; i++) {
1676 char name[12];
1677
1678 sprintf(name, "st,pll@%d", i);
1679 plloff[i] = dev_read_subnode(dev, name);
1680 if (!ofnode_valid(plloff[i]))
1681 continue;
1682 ret = ofnode_read_u32_array(plloff[i], "cfg",
1683 pllcfg[i], PLLCFG_NB);
1684 if (ret < 0) {
1685 debug("field cfg invalid: error %d\n", ret);
1686 return -FDT_ERR_NOTFOUND;
1687 }
1688 }
1689
1690 debug("configuration MCO\n");
1691 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1692 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1693
1694 debug("switch ON osillator\n");
1695
1696
1697
1698
1699 if (priv->osc[_LSI])
1700 stm32mp1_lsi_set(rcc, 1);
1701
1702 if (priv->osc[_LSE]) {
1703 int bypass, digbyp, lsedrv;
1704 struct udevice *dev = priv->osc_dev[_LSE];
1705
1706 bypass = dev_read_bool(dev, "st,bypass");
1707 digbyp = dev_read_bool(dev, "st,digbypass");
1708 lse_css = dev_read_bool(dev, "st,css");
1709 lsedrv = dev_read_u32_default(dev, "st,drive",
1710 LSEDRV_MEDIUM_HIGH);
1711
1712 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1713 }
1714
1715 if (priv->osc[_HSE]) {
1716 int bypass, digbyp, css;
1717 struct udevice *dev = priv->osc_dev[_HSE];
1718
1719 bypass = dev_read_bool(dev, "st,bypass");
1720 digbyp = dev_read_bool(dev, "st,digbypass");
1721 css = dev_read_bool(dev, "st,css");
1722
1723 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1724 }
1725
1726
1727
1728 stm32mp1_csi_set(rcc, 1);
1729
1730
1731 debug("come back to HSI\n");
1732 set_clksrc(priv, CLK_MPU_HSI);
1733 set_clksrc(priv, CLK_AXI_HSI);
1734 set_clksrc(priv, CLK_MCU_HSI);
1735
1736 debug("pll stop\n");
1737 for (i = 0; i < _PLL_NB; i++)
1738 pll_stop(priv, i);
1739
1740
1741 debug("configure HSIDIV\n");
1742 if (priv->osc[_HSI]) {
1743 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1744 stgen_config(priv);
1745 }
1746
1747
1748 debug("select DIV\n");
1749
1750 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1751 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1752 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1753 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1754 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1755 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1756 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1757 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1758
1759
1760 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1761
1762
1763 debug("configure PLLs source\n");
1764 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1765 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1766 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1767
1768
1769 debug("configure PLLs\n");
1770 for (i = 0; i < _PLL_NB; i++) {
1771 u32 fracv;
1772 u32 csg[PLLCSG_NB];
1773
1774 debug("configure PLL %d @ %d\n", i,
1775 ofnode_to_offset(plloff[i]));
1776 if (!ofnode_valid(plloff[i]))
1777 continue;
1778
1779 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1780 pll_config(priv, i, pllcfg[i], fracv);
1781 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1782 if (!ret) {
1783 pll_csg(priv, i, csg);
1784 } else if (ret != -FDT_ERR_NOTFOUND) {
1785 debug("invalid csg node for pll@%d res=%d\n", i, ret);
1786 return ret;
1787 }
1788 pll_start(priv, i);
1789 }
1790
1791
1792 for (i = 0; i < _PLL_NB; i++) {
1793 if (!ofnode_valid(plloff[i]))
1794 continue;
1795 debug("output PLL %d\n", i);
1796 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1797 }
1798
1799
1800 if (priv->osc[_LSE])
1801 stm32mp1_lse_wait(rcc);
1802
1803
1804 debug("CLKSRC\n");
1805 set_clksrc(priv, clksrc[CLKSRC_MPU]);
1806 set_clksrc(priv, clksrc[CLKSRC_AXI]);
1807 set_clksrc(priv, clksrc[CLKSRC_MCU]);
1808 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1809
1810
1811 debug("PKCK\n");
1812 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1813 if (pkcs_cell) {
1814 bool ckper_disabled = false;
1815
1816 for (i = 0; i < len / sizeof(u32); i++) {
1817 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1818
1819 if (pkcs == CLK_CKPER_DISABLED) {
1820 ckper_disabled = true;
1821 continue;
1822 }
1823 pkcs_config(priv, pkcs);
1824 }
1825
1826
1827
1828
1829
1830 if (ckper_disabled)
1831 pkcs_config(priv, CLK_CKPER_DISABLED);
1832 }
1833
1834
1835 stgen_config(priv);
1836
1837 debug("oscillator off\n");
1838
1839 if (!priv->osc[_HSI])
1840 stm32mp1_hsi_set(rcc, 0);
1841
1842
1843 clrsetbits_le32(priv->base + RCC_DDRITFCR,
1844 RCC_DDRITFCR_DDRCKMOD_MASK,
1845 RCC_DDRITFCR_DDRCKMOD_SSR <<
1846 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1847
1848 return 0;
1849}
1850#endif
1851
1852static int pll_set_output_rate(struct udevice *dev,
1853 int pll_id,
1854 int div_id,
1855 unsigned long clk_rate)
1856{
1857 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1858 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1859 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1860 int div;
1861 ulong fvco;
1862
1863 if (div_id > _DIV_NB)
1864 return -EINVAL;
1865
1866 fvco = pll_get_fvco(priv, pll_id);
1867
1868 if (fvco <= clk_rate)
1869 div = 1;
1870 else
1871 div = DIV_ROUND_UP(fvco, clk_rate);
1872
1873 if (div > 128)
1874 div = 128;
1875
1876 debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1877
1878 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1879
1880 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1881 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1882 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1883
1884 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1885
1886 return 0;
1887}
1888
1889static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1890{
1891 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1892 int p;
1893
1894 switch (clk->id) {
1895#if defined(STM32MP1_CLOCK_TREE_INIT) && \
1896 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1897 case DDRPHYC:
1898 break;
1899#endif
1900 case LTDC_PX:
1901 case DSI_PX:
1902 break;
1903 default:
1904 pr_err("not supported");
1905 return -EINVAL;
1906 }
1907
1908 p = stm32mp1_clk_get_parent(priv, clk->id);
1909 if (p < 0)
1910 return -EINVAL;
1911
1912 switch (p) {
1913#if defined(STM32MP1_CLOCK_TREE_INIT) && \
1914 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1915 case _PLL2_R:
1916 {
1917
1918 ulong result;
1919
1920 set_clksrc(priv, CLK_AXI_HSI);
1921 result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
1922 set_clksrc(priv, CLK_AXI_PLL2P);
1923 return result;
1924 }
1925#endif
1926 case _PLL4_Q:
1927
1928 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1929 }
1930
1931 return -EINVAL;
1932}
1933
1934static void stm32mp1_osc_clk_init(const char *name,
1935 struct stm32mp1_clk_priv *priv,
1936 int index)
1937{
1938 struct clk clk;
1939 struct udevice *dev = NULL;
1940
1941 priv->osc[index] = 0;
1942 clk.id = 0;
1943 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1944 if (clk_request(dev, &clk))
1945 pr_err("%s request", name);
1946 else
1947 priv->osc[index] = clk_get_rate(&clk);
1948 }
1949 priv->osc_dev[index] = dev;
1950}
1951
1952static void stm32mp1_osc_init(struct udevice *dev)
1953{
1954 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1955 int i;
1956 const char *name[NB_OSC] = {
1957 [_LSI] = "clk-lsi",
1958 [_LSE] = "clk-lse",
1959 [_HSI] = "clk-hsi",
1960 [_HSE] = "clk-hse",
1961 [_CSI] = "clk-csi",
1962 [_I2S_CKIN] = "i2s_ckin",
1963 };
1964
1965 for (i = 0; i < NB_OSC; i++) {
1966 stm32mp1_osc_clk_init(name[i], priv, i);
1967 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1968 }
1969}
1970
1971static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1972{
1973 char buf[32];
1974 int i, s, p;
1975
1976 printf("Clocks:\n");
1977 for (i = 0; i < _PARENT_NB; i++) {
1978 printf("- %s : %s MHz\n",
1979 stm32mp1_clk_parent_name[i],
1980 strmhz(buf, stm32mp1_clk_get(priv, i)));
1981 }
1982 printf("Source Clocks:\n");
1983 for (i = 0; i < _PARENT_SEL_NB; i++) {
1984 p = (readl(priv->base + priv->data->sel[i].offset) >>
1985 priv->data->sel[i].src) & priv->data->sel[i].msk;
1986 if (p < priv->data->sel[i].nb_parent) {
1987 s = priv->data->sel[i].parent[p];
1988 printf("- %s(%d) => parent %s(%d)\n",
1989 stm32mp1_clk_parent_sel_name[i], i,
1990 stm32mp1_clk_parent_name[s], s);
1991 } else {
1992 printf("- %s(%d) => parent index %d is invalid\n",
1993 stm32mp1_clk_parent_sel_name[i], i, p);
1994 }
1995 }
1996}
1997
1998#ifdef CONFIG_CMD_CLK
1999int soc_clk_dump(void)
2000{
2001 struct udevice *dev;
2002 struct stm32mp1_clk_priv *priv;
2003 int ret;
2004
2005 ret = uclass_get_device_by_driver(UCLASS_CLK,
2006 DM_GET_DRIVER(stm32mp1_clock),
2007 &dev);
2008 if (ret)
2009 return ret;
2010
2011 priv = dev_get_priv(dev);
2012
2013 stm32mp1_clk_dump(priv);
2014
2015 return 0;
2016}
2017#endif
2018
2019static int stm32mp1_clk_probe(struct udevice *dev)
2020{
2021 int result = 0;
2022 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2023
2024 priv->base = dev_read_addr(dev->parent);
2025 if (priv->base == FDT_ADDR_T_NONE)
2026 return -EINVAL;
2027
2028 priv->data = (void *)&stm32mp1_data;
2029
2030 if (!priv->data->gate || !priv->data->sel ||
2031 !priv->data->pll)
2032 return -EINVAL;
2033
2034 stm32mp1_osc_init(dev);
2035
2036#ifdef STM32MP1_CLOCK_TREE_INIT
2037
2038 if (!(gd->flags & GD_FLG_RELOC))
2039 result = stm32mp1_clktree(dev);
2040#endif
2041
2042#ifndef CONFIG_SPL_BUILD
2043#if defined(DEBUG)
2044
2045 if (gd->flags & GD_FLG_RELOC)
2046 stm32mp1_clk_dump(priv);
2047#endif
2048
2049#if defined(CONFIG_DISPLAY_CPUINFO)
2050 if (gd->flags & GD_FLG_RELOC) {
2051 char buf[32];
2052
2053 printf("Clocks:\n");
2054 printf("- MPU : %s MHz\n",
2055 strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
2056 printf("- MCU : %s MHz\n",
2057 strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2058 printf("- AXI : %s MHz\n",
2059 strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
2060 printf("- PER : %s MHz\n",
2061 strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2062
2063 printf("- DDR : %s MHz\n",
2064 strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
2065 }
2066#endif
2067#endif
2068
2069 return result;
2070}
2071
2072static const struct clk_ops stm32mp1_clk_ops = {
2073 .enable = stm32mp1_clk_enable,
2074 .disable = stm32mp1_clk_disable,
2075 .get_rate = stm32mp1_clk_get_rate,
2076 .set_rate = stm32mp1_clk_set_rate,
2077};
2078
2079U_BOOT_DRIVER(stm32mp1_clock) = {
2080 .name = "stm32mp1_clk",
2081 .id = UCLASS_CLK,
2082 .ops = &stm32mp1_clk_ops,
2083 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2084 .probe = stm32mp1_clk_probe,
2085};
2086
