LXR uboot/drivers/clk/tegra/tegra-car-clk.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2016, NVIDIA CORPORATION.
   4 */
   5
   6#include <common.h>
   7#include <clk-uclass.h>
   8#include <dm.h>
   9#include <asm/arch/clock.h>
  10#include <asm/arch-tegra/clk_rst.h>
  11
  12static int tegra_car_clk_request(struct clk *clk)
  13{
  14        debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  15              clk->id);
  16
  17        /*
  18         * Note that the first PERIPH_ID_COUNT clock IDs (where the value
  19         * varies per SoC) are the peripheral clocks, which use a numbering
  20         * scheme that matches HW registers 1:1. There are other clock IDs
  21         * beyond this that are assigned arbitrarily by the Tegra CAR DT
  22         * binding. Due to the implementation of this driver, it currently
  23         * only supports the peripheral IDs.
  24         */
  25        if (clk->id >= PERIPH_ID_COUNT)
  26                return -EINVAL;
  27
  28        return 0;
  29}
  30
  31static int tegra_car_clk_free(struct clk *clk)
  32{
  33        debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  34              clk->id);
  35
  36        return 0;
  37}
  38
  39static ulong tegra_car_clk_get_rate(struct clk *clk)
  40{
  41        enum clock_id parent;
  42
  43        debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  44              clk->id);
  45
  46        parent = clock_get_periph_parent(clk->id);
  47        return clock_get_periph_rate(clk->id, parent);
  48}
  49
  50static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
  51{
  52        enum clock_id parent;
  53
  54        debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
  55              clk->dev, clk->id);
  56
  57        parent = clock_get_periph_parent(clk->id);
  58        return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
  59}
  60
  61static int tegra_car_clk_enable(struct clk *clk)
  62{
  63        debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  64              clk->id);
  65
  66        clock_enable(clk->id);
  67
  68        return 0;
  69}
  70
  71static int tegra_car_clk_disable(struct clk *clk)
  72{
  73        debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  74              clk->id);
  75
  76        clock_disable(clk->id);
  77
  78        return 0;
  79}
  80
  81static struct clk_ops tegra_car_clk_ops = {
  82        .request = tegra_car_clk_request,
  83        .free = tegra_car_clk_free,
  84        .get_rate = tegra_car_clk_get_rate,
  85        .set_rate = tegra_car_clk_set_rate,
  86        .enable = tegra_car_clk_enable,
  87        .disable = tegra_car_clk_disable,
  88};
  89
  90static int tegra_car_clk_probe(struct udevice *dev)
  91{
  92        debug("%s(dev=%p)\n", __func__, dev);
  93
  94        return 0;
  95}
  96
  97U_BOOT_DRIVER(tegra_car_clk) = {
  98        .name = "tegra_car_clk",
  99        .id = UCLASS_CLK,
 100        .probe = tegra_car_clk_probe,
 101        .ops = &tegra_car_clk_ops,
 102};
 103