LXR uboot/drivers/ddr/fsl/main.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4 */
   5
   6/*
   7 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   8 * Based on code from spd_sdram.c
   9 * Author: James Yang [at freescale.com]
  10 */
  11
  12#include <common.h>
  13#include <i2c.h>
  14#include <fsl_ddr_sdram.h>
  15#include <fsl_ddr.h>
  16
  17/*
  18 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  19 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
  20 * all Power SoCs. But it could be different for ARM SoCs. For example,
  21 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  22 * 0x00_8000_0000 ~ 0x00_ffff_ffff
  23 * 0x80_8000_0000 ~ 0xff_ffff_ffff
  24 */
  25#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
  26#ifdef CONFIG_MPC83xx
  27#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
  28#else
  29#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
  30#endif
  31#endif
  32
  33#ifdef CONFIG_PPC
  34#include <asm/fsl_law.h>
  35
  36void fsl_ddr_set_lawbar(
  37                const common_timing_params_t *memctl_common_params,
  38                unsigned int memctl_interleaved,
  39                unsigned int ctrl_num);
  40#endif
  41
  42void fsl_ddr_set_intl3r(const unsigned int granule_size);
  43#if defined(SPD_EEPROM_ADDRESS) || \
  44    defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  45    defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  46#if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  47u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  48        [0][0] = SPD_EEPROM_ADDRESS,
  49};
  50#elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  51u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  52        [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  53        [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  54};
  55#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  56u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  57        [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  58        [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  59};
  60#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  61u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  62        [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  63        [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  64        [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  65        [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  66};
  67#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  68u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  69        [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  70        [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  71        [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  72};
  73#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  74u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  75        [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  76        [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  77        [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  78        [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  79        [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  80        [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  81};
  82
  83#endif
  84
  85#define SPD_SPA0_ADDRESS        0x36
  86#define SPD_SPA1_ADDRESS        0x37
  87
  88static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  89{
  90        int ret;
  91#ifdef CONFIG_SYS_FSL_DDR4
  92        uint8_t dummy = 0;
  93#endif
  94
  95        i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  96
  97#ifdef CONFIG_SYS_FSL_DDR4
  98        /*
  99         * DDR4 SPD has 384 to 512 bytes
 100         * To access the lower 256 bytes, we need to set EE page address to 0
 101         * To access the upper 256 bytes, we need to set EE page address to 1
 102         * See Jedec standar No. 21-C for detail
 103         */
 104        i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
 105        ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
 106        if (!ret) {
 107                i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
 108                ret = i2c_read(i2c_address, 0, 1,
 109                               (uchar *)((ulong)spd + 256),
 110                               min(256,
 111                                   (int)sizeof(generic_spd_eeprom_t) - 256));
 112        }
 113#else
 114        ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
 115                                sizeof(generic_spd_eeprom_t));
 116#endif
 117
 118        if (ret) {
 119                if (i2c_address ==
 120#ifdef SPD_EEPROM_ADDRESS
 121                                SPD_EEPROM_ADDRESS
 122#elif defined(SPD_EEPROM_ADDRESS1)
 123                                SPD_EEPROM_ADDRESS1
 124#endif
 125                                ) {
 126                        printf("DDR: failed to read SPD from address %u\n",
 127                                i2c_address);
 128                } else {
 129                        debug("DDR: failed to read SPD from address %u\n",
 130                                i2c_address);
 131                }
 132                memset(spd, 0, sizeof(generic_spd_eeprom_t));
 133        }
 134}
 135
 136__attribute__((weak, alias("__get_spd")))
 137void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 138
 139/* This function allows boards to update SPD address */
 140__weak void update_spd_address(unsigned int ctrl_num,
 141                               unsigned int slot,
 142                               unsigned int *addr)
 143{
 144}
 145
 146void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 147                      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 148{
 149        unsigned int i;
 150        unsigned int i2c_address = 0;
 151
 152        if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
 153                printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 154                return;
 155        }
 156
 157        for (i = 0; i < dimm_slots_per_ctrl; i++) {
 158                i2c_address = spd_i2c_addr[ctrl_num][i];
 159                update_spd_address(ctrl_num, i, &i2c_address);
 160                get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 161        }
 162}
 163#else
 164void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 165                      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 166{
 167}
 168#endif /* SPD_EEPROM_ADDRESSx */
 169
 170/*
 171 * ASSUMPTIONS:
 172 *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 173 *    - Same memory data bus width on all controllers
 174 *
 175 * NOTES:
 176 *
 177 * The memory controller and associated documentation use confusing
 178 * terminology when referring to the orgranization of DRAM.
 179 *
 180 * Here is a terminology translation table:
 181 *
 182 * memory controller/documention  |industry   |this code  |signals
 183 * -------------------------------|-----------|-----------|-----------------
 184 * physical bank/bank             |rank       |rank       |chip select (CS)
 185 * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 186 * page/row                       |row        |page       |row address
 187 * ???                            |column     |column     |column address
 188 *
 189 * The naming confusion is further exacerbated by the descriptions of the
 190 * memory controller interleaving feature, where accesses are interleaved
 191 * _BETWEEN_ two seperate memory controllers.  This is configured only in
 192 * CS0_CONFIG[INTLV_CTL] of each memory controller.
 193 *
 194 * memory controller documentation | number of chip selects
 195 *                                 | per memory controller supported
 196 * --------------------------------|-----------------------------------------
 197 * cache line interleaving         | 1 (CS0 only)
 198 * page interleaving               | 1 (CS0 only)
 199 * bank interleaving               | 1 (CS0 only)
 200 * superbank interleraving         | depends on bank (chip select)
 201 *                                 |   interleraving [rank interleaving]
 202 *                                 |   mode used on every memory controller
 203 *
 204 * Even further confusing is the existence of the interleaving feature
 205 * _WITHIN_ each memory controller.  The feature is referred to in
 206 * documentation as chip select interleaving or bank interleaving,
 207 * although it is configured in the DDR_SDRAM_CFG field.
 208 *
 209 * Name of field                | documentation name    | this code
 210 * -----------------------------|-----------------------|------------------
 211 * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 212 *                              |  interleaving
 213 */
 214
 215const char *step_string_tbl[] = {
 216        "STEP_GET_SPD",
 217        "STEP_COMPUTE_DIMM_PARMS",
 218        "STEP_COMPUTE_COMMON_PARMS",
 219        "STEP_GATHER_OPTS",
 220        "STEP_ASSIGN_ADDRESSES",
 221        "STEP_COMPUTE_REGS",
 222        "STEP_PROGRAM_REGS",
 223        "STEP_ALL"
 224};
 225
 226const char * step_to_string(unsigned int step) {
 227
 228        unsigned int s = __ilog2(step);
 229
 230        if ((1 << s) != step)
 231                return step_string_tbl[7];
 232
 233        if (s >= ARRAY_SIZE(step_string_tbl)) {
 234                printf("Error for the step in %s\n", __func__);
 235                s = 0;
 236        }
 237
 238        return step_string_tbl[s];
 239}
 240
 241static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 242                          unsigned int dbw_cap_adj[])
 243{
 244        unsigned int i, j;
 245        unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 246        unsigned long long rank_density, ctlr_density = 0;
 247        unsigned int first_ctrl = pinfo->first_ctrl;
 248        unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 249
 250        /*
 251         * If a reduced data width is requested, but the SPD
 252         * specifies a physically wider device, adjust the
 253         * computed dimm capacities accordingly before
 254         * assigning addresses.
 255         */
 256        for (i = first_ctrl; i <= last_ctrl; i++) {
 257                unsigned int found = 0;
 258
 259                switch (pinfo->memctl_opts[i].data_bus_width) {
 260                case 2:
 261                        /* 16-bit */
 262                        for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 263                                unsigned int dw;
 264                                if (!pinfo->dimm_params[i][j].n_ranks)
 265                                        continue;
 266                                dw = pinfo->dimm_params[i][j].primary_sdram_width;
 267                                if ((dw == 72 || dw == 64)) {
 268                                        dbw_cap_adj[i] = 2;
 269                                        break;
 270                                } else if ((dw == 40 || dw == 32)) {
 271                                        dbw_cap_adj[i] = 1;
 272                                        break;
 273                                }
 274                        }
 275                        break;
 276
 277                case 1:
 278                        /* 32-bit */
 279                        for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 280                                unsigned int dw;
 281                                dw = pinfo->dimm_params[i][j].data_width;
 282                                if (pinfo->dimm_params[i][j].n_ranks
 283                                    && (dw == 72 || dw == 64)) {
 284                                        /*
 285                                         * FIXME: can't really do it
 286                                         * like this because this just
 287                                         * further reduces the memory
 288                                         */
 289                                        found = 1;
 290                                        break;
 291                                }
 292                        }
 293                        if (found) {
 294                                dbw_cap_adj[i] = 1;
 295                        }
 296                        break;
 297
 298                case 0:
 299                        /* 64-bit */
 300                        break;
 301
 302                default:
 303                        printf("unexpected data bus width "
 304                                "specified controller %u\n", i);
 305                        return 1;
 306                }
 307                debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 308        }
 309
 310        current_mem_base = pinfo->mem_base;
 311        total_mem = 0;
 312        if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
 313                rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
 314                                        dbw_cap_adj[first_ctrl];
 315                switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
 316                                        FSL_DDR_CS0_CS1_CS2_CS3) {
 317                case FSL_DDR_CS0_CS1_CS2_CS3:
 318                        ctlr_density = 4 * rank_density;
 319                        break;
 320                case FSL_DDR_CS0_CS1:
 321                case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 322                        ctlr_density = 2 * rank_density;
 323                        break;
 324                case FSL_DDR_CS2_CS3:
 325                default:
 326                        ctlr_density = rank_density;
 327                        break;
 328                }
 329                debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 330                        rank_density, ctlr_density);
 331                for (i = first_ctrl; i <= last_ctrl; i++) {
 332                        if (pinfo->memctl_opts[i].memctl_interleaving) {
 333                                switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 334                                case FSL_DDR_256B_INTERLEAVING:
 335                                case FSL_DDR_CACHE_LINE_INTERLEAVING:
 336                                case FSL_DDR_PAGE_INTERLEAVING:
 337                                case FSL_DDR_BANK_INTERLEAVING:
 338                                case FSL_DDR_SUPERBANK_INTERLEAVING:
 339                                        total_ctlr_mem = 2 * ctlr_density;
 340                                        break;
 341                                case FSL_DDR_3WAY_1KB_INTERLEAVING:
 342                                case FSL_DDR_3WAY_4KB_INTERLEAVING:
 343                                case FSL_DDR_3WAY_8KB_INTERLEAVING:
 344                                        total_ctlr_mem = 3 * ctlr_density;
 345                                        break;
 346                                case FSL_DDR_4WAY_1KB_INTERLEAVING:
 347                                case FSL_DDR_4WAY_4KB_INTERLEAVING:
 348                                case FSL_DDR_4WAY_8KB_INTERLEAVING:
 349                                        total_ctlr_mem = 4 * ctlr_density;
 350                                        break;
 351                                default:
 352                                        panic("Unknown interleaving mode");
 353                                }
 354                                pinfo->common_timing_params[i].base_address =
 355                                                        current_mem_base;
 356                                pinfo->common_timing_params[i].total_mem =
 357                                                        total_ctlr_mem;
 358                                total_mem = current_mem_base + total_ctlr_mem;
 359                                debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 360                                debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 361                        } else {
 362                                /* when 3rd controller not interleaved */
 363                                current_mem_base = total_mem;
 364                                total_ctlr_mem = 0;
 365                                pinfo->common_timing_params[i].base_address =
 366                                                        current_mem_base;
 367                                for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 368                                        unsigned long long cap =
 369                                                pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 370                                        pinfo->dimm_params[i][j].base_address =
 371                                                current_mem_base;
 372                                        debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 373                                        current_mem_base += cap;
 374                                        total_ctlr_mem += cap;
 375                                }
 376                                debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 377                                pinfo->common_timing_params[i].total_mem =
 378                                                        total_ctlr_mem;
 379                                total_mem += total_ctlr_mem;
 380                        }
 381                }
 382        } else {
 383                /*
 384                 * Simple linear assignment if memory
 385                 * controllers are not interleaved.
 386                 */
 387                for (i = first_ctrl; i <= last_ctrl; i++) {
 388                        total_ctlr_mem = 0;
 389                        pinfo->common_timing_params[i].base_address =
 390                                                current_mem_base;
 391                        for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 392                                /* Compute DIMM base addresses. */
 393                                unsigned long long cap =
 394                                        pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 395                                pinfo->dimm_params[i][j].base_address =
 396                                        current_mem_base;
 397                                debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 398                                current_mem_base += cap;
 399                                total_ctlr_mem += cap;
 400                        }
 401                        debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 402                        pinfo->common_timing_params[i].total_mem =
 403                                                        total_ctlr_mem;
 404                        total_mem += total_ctlr_mem;
 405                }
 406        }
 407        debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 408
 409        return total_mem;
 410}
 411
 412/* Use weak function to allow board file to override the address assignment */
 413__attribute__((weak, alias("__step_assign_addresses")))
 414unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 415                          unsigned int dbw_cap_adj[]);
 416
 417unsigned long long
 418fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 419                                       unsigned int size_only)
 420{
 421        unsigned int i, j;
 422        unsigned long long total_mem = 0;
 423        int assert_reset = 0;
 424        unsigned int first_ctrl =  pinfo->first_ctrl;
 425        unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 426        __maybe_unused int retval;
 427        __maybe_unused bool goodspd = false;
 428        __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
 429
 430        fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 431        common_timing_params_t *timing_params = pinfo->common_timing_params;
 432        if (pinfo->board_need_mem_reset)
 433                assert_reset = pinfo->board_need_mem_reset();
 434
 435        /* data bus width capacity adjust shift amount */
 436        unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
 437
 438        for (i = first_ctrl; i <= last_ctrl; i++)
 439                dbw_capacity_adjust[i] = 0;
 440
 441        debug("starting at step %u (%s)\n",
 442              start_step, step_to_string(start_step));
 443
 444        switch (start_step) {
 445        case STEP_GET_SPD:
 446#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 447                /* STEP 1:  Gather all DIMM SPD data */
 448                for (i = first_ctrl; i <= last_ctrl; i++) {
 449                        fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
 450                                        dimm_slots_per_ctrl);
 451                }
 452
 453        case STEP_COMPUTE_DIMM_PARMS:
 454                /* STEP 2:  Compute DIMM parameters from SPD data */
 455
 456                for (i = first_ctrl; i <= last_ctrl; i++) {
 457                        for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 458                                generic_spd_eeprom_t *spd =
 459                                        &(pinfo->spd_installed_dimms[i][j]);
 460                                dimm_params_t *pdimm =
 461                                        &(pinfo->dimm_params[i][j]);
 462                                retval = compute_dimm_parameters(
 463                                                        i, spd, pdimm, j);
 464#ifdef CONFIG_SYS_DDR_RAW_TIMING
 465                                if (!j && retval) {
 466                                        printf("SPD error on controller %d! "
 467                                        "Trying fallback to raw timing "
 468                                        "calculation\n", i);
 469                                        retval = fsl_ddr_get_dimm_params(pdimm,
 470                                                                         i, j);
 471                                }
 472#else
 473                                if (retval == 2) {
 474                                        printf("Error: compute_dimm_parameters"
 475                                        " non-zero returned FATAL value "
 476                                        "for memctl=%u dimm=%u\n", i, j);
 477                                        return 0;
 478                                }
 479#endif
 480                                if (retval) {
 481                                        debug("Warning: compute_dimm_parameters"
 482                                        " non-zero return value for memctl=%u "
 483                                        "dimm=%u\n", i, j);
 484                                } else {
 485                                        goodspd = true;
 486                                }
 487                        }
 488                }
 489                if (!goodspd) {
 490                        /*
 491                         * No valid SPD found
 492                         * Throw an error if this is for main memory, i.e.
 493                         * first_ctrl == 0. Otherwise, siliently return 0
 494                         * as the memory size.
 495                         */
 496                        if (first_ctrl == 0)
 497                                printf("Error: No valid SPD detected.\n");
 498
 499                        return 0;
 500                }
 501#elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 502        case STEP_COMPUTE_DIMM_PARMS:
 503                for (i = first_ctrl; i <= last_ctrl; i++) {
 504                        for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 505                                dimm_params_t *pdimm =
 506                                        &(pinfo->dimm_params[i][j]);
 507                                fsl_ddr_get_dimm_params(pdimm, i, j);
 508                        }
 509                }
 510                debug("Filling dimm parameters from board specific file\n");
 511#endif
 512        case STEP_COMPUTE_COMMON_PARMS:
 513                /*
 514                 * STEP 3: Compute a common set of timing parameters
 515                 * suitable for all of the DIMMs on each memory controller
 516                 */
 517                for (i = first_ctrl; i <= last_ctrl; i++) {
 518                        debug("Computing lowest common DIMM"
 519                                " parameters for memctl=%u\n", i);
 520                        compute_lowest_common_dimm_parameters
 521                                (i,
 522                                 pinfo->dimm_params[i],
 523                                 &timing_params[i],
 524                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 525                }
 526
 527        case STEP_GATHER_OPTS:
 528                /* STEP 4:  Gather configuration requirements from user */
 529                for (i = first_ctrl; i <= last_ctrl; i++) {
 530                        debug("Reloading memory controller "
 531                                "configuration options for memctl=%u\n", i);
 532                        /*
 533                         * This "reloads" the memory controller options
 534                         * to defaults.  If the user "edits" an option,
 535                         * next_step points to the step after this,
 536                         * which is currently STEP_ASSIGN_ADDRESSES.
 537                         */
 538                        populate_memctl_options(
 539                                        &timing_params[i],
 540                                        &pinfo->memctl_opts[i],
 541                                        pinfo->dimm_params[i], i);
 542                        /*
 543                         * For RDIMMs, JEDEC spec requires clocks to be stable
 544                         * before reset signal is deasserted. For the boards
 545                         * using fixed parameters, this function should be
 546                         * be called from board init file.
 547                         */
 548                        if (timing_params[i].all_dimms_registered)
 549                                assert_reset = 1;
 550                }
 551                if (assert_reset && !size_only) {
 552                        if (pinfo->board_mem_reset) {
 553                                debug("Asserting mem reset\n");
 554                                pinfo->board_mem_reset();
 555                        } else {
 556                                debug("Asserting mem reset missing\n");
 557                        }
 558                }
 559
 560        case STEP_ASSIGN_ADDRESSES:
 561                /* STEP 5:  Assign addresses to chip selects */
 562                check_interleaving_options(pinfo);
 563                total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 564                debug("Total mem %llu assigned\n", total_mem);
 565
 566        case STEP_COMPUTE_REGS:
 567                /* STEP 6:  compute controller register values */
 568                debug("FSL Memory ctrl register computation\n");
 569                for (i = first_ctrl; i <= last_ctrl; i++) {
 570                        if (timing_params[i].ndimms_present == 0) {
 571                                memset(&ddr_reg[i], 0,
 572                                        sizeof(fsl_ddr_cfg_regs_t));
 573                                continue;
 574                        }
 575
 576                        compute_fsl_memctl_config_regs
 577                                (i,
 578                                 &pinfo->memctl_opts[i],
 579                                 &ddr_reg[i], &timing_params[i],
 580                                 pinfo->dimm_params[i],
 581                                 dbw_capacity_adjust[i],
 582                                 size_only);
 583                }
 584
 585        default:
 586                break;
 587        }
 588
 589        {
 590                /*
 591                 * Compute the amount of memory available just by
 592                 * looking for the highest valid CSn_BNDS value.
 593                 * This allows us to also experiment with using
 594                 * only CS0 when using dual-rank DIMMs.
 595                 */
 596                unsigned int max_end = 0;
 597
 598                for (i = first_ctrl; i <= last_ctrl; i++) {
 599                        for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 600                                fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 601                                if (reg->cs[j].config & 0x80000000) {
 602                                        unsigned int end;
 603                                        /*
 604                                         * 0xfffffff is a special value we put
 605                                         * for unused bnds
 606                                         */
 607                                        if (reg->cs[j].bnds == 0xffffffff)
 608                                                continue;
 609                                        end = reg->cs[j].bnds & 0xffff;
 610                                        if (end > max_end) {
 611                                                max_end = end;
 612                                        }
 613                                }
 614                        }
 615                }
 616
 617                total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
 618                            0xFFFFFFULL) - pinfo->mem_base;
 619        }
 620
 621        return total_mem;
 622}
 623
 624phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 625{
 626        unsigned int i, first_ctrl, last_ctrl;
 627#ifdef CONFIG_PPC
 628        unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 629#endif
 630        unsigned long long total_memory;
 631        int deassert_reset = 0;
 632
 633        first_ctrl = pinfo->first_ctrl;
 634        last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 635
 636        /* Compute it once normally. */
 637#ifdef CONFIG_FSL_DDR_INTERACTIVE
 638        if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 639                total_memory = fsl_ddr_interactive(pinfo, 0);
 640        } else if (fsl_ddr_interactive_env_var_exists()) {
 641                total_memory = fsl_ddr_interactive(pinfo, 1);
 642        } else
 643#endif
 644                total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
 645
 646        /* setup 3-way interleaving before enabling DDRC */
 647        switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
 648        case FSL_DDR_3WAY_1KB_INTERLEAVING:
 649        case FSL_DDR_3WAY_4KB_INTERLEAVING:
 650        case FSL_DDR_3WAY_8KB_INTERLEAVING:
 651                fsl_ddr_set_intl3r(
 652                        pinfo->memctl_opts[first_ctrl].
 653                        memctl_interleaving_mode);
 654                break;
 655        default:
 656                break;
 657        }
 658
 659        /*
 660         * Program configuration registers.
 661         * JEDEC specs requires clocks to be stable before deasserting reset
 662         * for RDIMMs. Clocks start after chip select is enabled and clock
 663         * control register is set. During step 1, all controllers have their
 664         * registers set but not enabled. Step 2 proceeds after deasserting
 665         * reset through board FPGA or GPIO.
 666         * For non-registered DIMMs, initialization can go through but it is
 667         * also OK to follow the same flow.
 668         */
 669        if (pinfo->board_need_mem_reset)
 670                deassert_reset = pinfo->board_need_mem_reset();
 671        for (i = first_ctrl; i <= last_ctrl; i++) {
 672                if (pinfo->common_timing_params[i].all_dimms_registered)
 673                        deassert_reset = 1;
 674        }
 675        for (i = first_ctrl; i <= last_ctrl; i++) {
 676                debug("Programming controller %u\n", i);
 677                if (pinfo->common_timing_params[i].ndimms_present == 0) {
 678                        debug("No dimms present on controller %u; "
 679                                        "skipping programming\n", i);
 680                        continue;
 681                }
 682                /*
 683                 * The following call with step = 1 returns before enabling
 684                 * the controller. It has to finish with step = 2 later.
 685                 */
 686                fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
 687                                        deassert_reset ? 1 : 0);
 688        }
 689        if (deassert_reset) {
 690                /* Use board FPGA or GPIO to deassert reset signal */
 691                if (pinfo->board_mem_de_reset) {
 692                        debug("Deasserting mem reset\n");
 693                        pinfo->board_mem_de_reset();
 694                } else {
 695                        debug("Deasserting mem reset missing\n");
 696                }
 697                for (i = first_ctrl; i <= last_ctrl; i++) {
 698                        /* Call with step = 2 to continue initialization */
 699                        fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
 700                                                i, 2);
 701                }
 702        }
 703
 704#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 705        fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
 706#endif
 707
 708#ifdef CONFIG_PPC
 709        /* program LAWs */
 710        for (i = first_ctrl; i <= last_ctrl; i++) {
 711                if (pinfo->memctl_opts[i].memctl_interleaving) {
 712                        switch (pinfo->memctl_opts[i].
 713                                memctl_interleaving_mode) {
 714                        case FSL_DDR_CACHE_LINE_INTERLEAVING:
 715                        case FSL_DDR_PAGE_INTERLEAVING:
 716                        case FSL_DDR_BANK_INTERLEAVING:
 717                        case FSL_DDR_SUPERBANK_INTERLEAVING:
 718                                if (i % 2)
 719                                        break;
 720                                if (i == 0) {
 721                                        law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 722                                        fsl_ddr_set_lawbar(
 723                                                &pinfo->common_timing_params[i],
 724                                                law_memctl, i);
 725                                }
 726#if CONFIG_SYS_NUM_DDR_CTLRS > 3
 727                                else if (i == 2) {
 728                                        law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 729                                        fsl_ddr_set_lawbar(
 730                                                &pinfo->common_timing_params[i],
 731                                                law_memctl, i);
 732                                }
 733#endif
 734                                break;
 735                        case FSL_DDR_3WAY_1KB_INTERLEAVING:
 736                        case FSL_DDR_3WAY_4KB_INTERLEAVING:
 737                        case FSL_DDR_3WAY_8KB_INTERLEAVING:
 738                                law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 739                                if (i == 0) {
 740                                        fsl_ddr_set_lawbar(
 741                                                &pinfo->common_timing_params[i],
 742                                                law_memctl, i);
 743                                }
 744                                break;
 745                        case FSL_DDR_4WAY_1KB_INTERLEAVING:
 746                        case FSL_DDR_4WAY_4KB_INTERLEAVING:
 747                        case FSL_DDR_4WAY_8KB_INTERLEAVING:
 748                                law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 749                                if (i == 0)
 750                                        fsl_ddr_set_lawbar(
 751                                                &pinfo->common_timing_params[i],
 752                                                law_memctl, i);
 753                                /* place holder for future 4-way interleaving */
 754                                break;
 755                        default:
 756                                break;
 757                        }
 758                } else {
 759                        switch (i) {
 760                        case 0:
 761                                law_memctl = LAW_TRGT_IF_DDR_1;
 762                                break;
 763                        case 1:
 764                                law_memctl = LAW_TRGT_IF_DDR_2;
 765                                break;
 766                        case 2:
 767                                law_memctl = LAW_TRGT_IF_DDR_3;
 768                                break;
 769                        case 3:
 770                                law_memctl = LAW_TRGT_IF_DDR_4;
 771                                break;
 772                        default:
 773                                break;
 774                        }
 775                        fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
 776                                           law_memctl, i);
 777                }
 778        }
 779#endif
 780
 781        debug("total_memory by %s = %llu\n", __func__, total_memory);
 782
 783#if !defined(CONFIG_PHYS_64BIT)
 784        /* Check for 4G or more.  Bad. */
 785        if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
 786                puts("Detected ");
 787                print_size(total_memory, " of memory\n");
 788                printf("       This U-Boot only supports < 4G of DDR\n");
 789                printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 790                printf("       "); /* re-align to match init_dram print */
 791                total_memory = CONFIG_MAX_MEM_MAPPED;
 792        }
 793#endif
 794
 795        return total_memory;
 796}
 797
 798/*
 799 * fsl_ddr_sdram(void) -- this is the main function to be
 800 * called by dram_init() in the board file.
 801 *
 802 * It returns amount of memory configured in bytes.
 803 */
 804phys_size_t fsl_ddr_sdram(void)
 805{
 806        fsl_ddr_info_t info;
 807
 808        /* Reset info structure. */
 809        memset(&info, 0, sizeof(fsl_ddr_info_t));
 810        info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 811        info.first_ctrl = 0;
 812        info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 813        info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 814        info.board_need_mem_reset = board_need_mem_reset;
 815        info.board_mem_reset = board_assert_mem_reset;
 816        info.board_mem_de_reset = board_deassert_mem_reset;
 817        remove_unused_controllers(&info);
 818
 819        return __fsl_ddr_sdram(&info);
 820}
 821
 822#ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 823phys_size_t fsl_other_ddr_sdram(unsigned long long base,
 824                                unsigned int first_ctrl,
 825                                unsigned int num_ctrls,
 826                                unsigned int dimm_slots_per_ctrl,
 827                                int (*board_need_reset)(void),
 828                                void (*board_reset)(void),
 829                                void (*board_de_reset)(void))
 830{
 831        fsl_ddr_info_t info;
 832
 833        /* Reset info structure. */
 834        memset(&info, 0, sizeof(fsl_ddr_info_t));
 835        info.mem_base = base;
 836        info.first_ctrl = first_ctrl;
 837        info.num_ctrls = num_ctrls;
 838        info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
 839        info.board_need_mem_reset = board_need_reset;
 840        info.board_mem_reset = board_reset;
 841        info.board_mem_de_reset = board_de_reset;
 842
 843        return __fsl_ddr_sdram(&info);
 844}
 845#endif
 846
 847/*
 848 * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
 849 * size of the total memory without setting ddr control registers.
 850 */
 851phys_size_t
 852fsl_ddr_sdram_size(void)
 853{
 854        fsl_ddr_info_t  info;
 855        unsigned long long total_memory = 0;
 856
 857        memset(&info, 0 , sizeof(fsl_ddr_info_t));
 858        info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 859        info.first_ctrl = 0;
 860        info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 861        info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 862        info.board_need_mem_reset = NULL;
 863        remove_unused_controllers(&info);
 864
 865        /* Compute it once normally. */
 866        total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 867
 868        return total_memory;
 869}
 870