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7#ifndef __DENALI_H__
8#define __DENALI_H__
9
10#include <linux/bitops.h>
11#include <linux/mtd/rawnand.h>
12#include <linux/types.h>
13#include <reset.h>
14
15#define DEVICE_RESET 0x0
16#define DEVICE_RESET__BANK(bank) BIT(bank)
17
18#define TRANSFER_SPARE_REG 0x10
19#define TRANSFER_SPARE_REG__FLAG BIT(0)
20
21#define LOAD_WAIT_CNT 0x20
22#define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
23
24#define PROGRAM_WAIT_CNT 0x30
25#define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
26
27#define ERASE_WAIT_CNT 0x40
28#define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
29
30#define INT_MON_CYCCNT 0x50
31#define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
32
33#define RB_PIN_ENABLED 0x60
34#define RB_PIN_ENABLED__BANK(bank) BIT(bank)
35
36#define MULTIPLANE_OPERATION 0x70
37#define MULTIPLANE_OPERATION__FLAG BIT(0)
38
39#define MULTIPLANE_READ_ENABLE 0x80
40#define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
41
42#define COPYBACK_DISABLE 0x90
43#define COPYBACK_DISABLE__FLAG BIT(0)
44
45#define CACHE_WRITE_ENABLE 0xa0
46#define CACHE_WRITE_ENABLE__FLAG BIT(0)
47
48#define CACHE_READ_ENABLE 0xb0
49#define CACHE_READ_ENABLE__FLAG BIT(0)
50
51#define PREFETCH_MODE 0xc0
52#define PREFETCH_MODE__PREFETCH_EN BIT(0)
53#define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
54
55#define CHIP_ENABLE_DONT_CARE 0xd0
56#define CHIP_EN_DONT_CARE__FLAG BIT(0)
57
58#define ECC_ENABLE 0xe0
59#define ECC_ENABLE__FLAG BIT(0)
60
61#define GLOBAL_INT_ENABLE 0xf0
62#define GLOBAL_INT_EN_FLAG BIT(0)
63
64#define TWHR2_AND_WE_2_RE 0x100
65#define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
66#define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
67
68#define TCWAW_AND_ADDR_2_DATA 0x110
69
70#define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
71#define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
72
73#define RE_2_WE 0x120
74#define RE_2_WE__VALUE GENMASK(5, 0)
75
76#define ACC_CLKS 0x130
77#define ACC_CLKS__VALUE GENMASK(3, 0)
78
79#define NUMBER_OF_PLANES 0x140
80#define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
81
82#define PAGES_PER_BLOCK 0x150
83#define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
84
85#define DEVICE_WIDTH 0x160
86#define DEVICE_WIDTH__VALUE GENMASK(1, 0)
87
88#define DEVICE_MAIN_AREA_SIZE 0x170
89#define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
90
91#define DEVICE_SPARE_AREA_SIZE 0x180
92#define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
93
94#define TWO_ROW_ADDR_CYCLES 0x190
95#define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
96
97#define MULTIPLANE_ADDR_RESTRICT 0x1a0
98#define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
99
100#define ECC_CORRECTION 0x1b0
101#define ECC_CORRECTION__VALUE GENMASK(4, 0)
102#define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16)
103
104#define READ_MODE 0x1c0
105#define READ_MODE__VALUE GENMASK(3, 0)
106
107#define WRITE_MODE 0x1d0
108#define WRITE_MODE__VALUE GENMASK(3, 0)
109
110#define COPYBACK_MODE 0x1e0
111#define COPYBACK_MODE__VALUE GENMASK(3, 0)
112
113#define RDWR_EN_LO_CNT 0x1f0
114#define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
115
116#define RDWR_EN_HI_CNT 0x200
117#define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
118
119#define MAX_RD_DELAY 0x210
120#define MAX_RD_DELAY__VALUE GENMASK(3, 0)
121
122#define CS_SETUP_CNT 0x220
123#define CS_SETUP_CNT__VALUE GENMASK(4, 0)
124#define CS_SETUP_CNT__TWB GENMASK(17, 12)
125
126#define SPARE_AREA_SKIP_BYTES 0x230
127#define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
128
129#define SPARE_AREA_MARKER 0x240
130#define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
131
132#define DEVICES_CONNECTED 0x250
133#define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
134
135#define DIE_MASK 0x260
136#define DIE_MASK__VALUE GENMASK(7, 0)
137
138#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
139#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
140
141#define WRITE_PROTECT 0x280
142#define WRITE_PROTECT__FLAG BIT(0)
143
144#define RE_2_RE 0x290
145#define RE_2_RE__VALUE GENMASK(5, 0)
146
147#define MANUFACTURER_ID 0x300
148#define MANUFACTURER_ID__VALUE GENMASK(7, 0)
149
150#define DEVICE_ID 0x310
151#define DEVICE_ID__VALUE GENMASK(7, 0)
152
153#define DEVICE_PARAM_0 0x320
154#define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
155
156#define DEVICE_PARAM_1 0x330
157#define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
158
159#define DEVICE_PARAM_2 0x340
160#define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
161
162#define LOGICAL_PAGE_DATA_SIZE 0x350
163#define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
164
165#define LOGICAL_PAGE_SPARE_SIZE 0x360
166#define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
167
168#define REVISION 0x370
169#define REVISION__VALUE GENMASK(15, 0)
170
171#define ONFI_DEVICE_FEATURES 0x380
172#define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
173
174#define ONFI_OPTIONAL_COMMANDS 0x390
175#define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
176
177#define ONFI_TIMING_MODE 0x3a0
178#define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
179
180#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
181#define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
182
183#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
184#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
185#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
186
187#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
188#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
189
190#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
191#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
192
193#define FEATURES 0x3f0
194#define FEATURES__N_BANKS GENMASK(1, 0)
195#define FEATURES__ECC_MAX_ERR GENMASK(5, 2)
196#define FEATURES__DMA BIT(6)
197#define FEATURES__CMD_DMA BIT(7)
198#define FEATURES__PARTITION BIT(8)
199#define FEATURES__XDMA_SIDEBAND BIT(9)
200#define FEATURES__GPREG BIT(10)
201#define FEATURES__INDEX_ADDR BIT(11)
202
203#define TRANSFER_MODE 0x400
204#define TRANSFER_MODE__VALUE GENMASK(1, 0)
205
206#define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
207#define INTR_EN(bank) (0x420 + (bank) * 0x50)
208
209#define INTR__ECC_UNCOR_ERR BIT(0)
210#define INTR__ECC_TRANSACTION_DONE BIT(0)
211#define INTR__ECC_ERR BIT(1)
212#define INTR__DMA_CMD_COMP BIT(2)
213#define INTR__TIME_OUT BIT(3)
214#define INTR__PROGRAM_FAIL BIT(4)
215#define INTR__ERASE_FAIL BIT(5)
216#define INTR__LOAD_COMP BIT(6)
217#define INTR__PROGRAM_COMP BIT(7)
218#define INTR__ERASE_COMP BIT(8)
219#define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
220#define INTR__LOCKED_BLK BIT(10)
221#define INTR__UNSUP_CMD BIT(11)
222#define INTR__INT_ACT BIT(12)
223#define INTR__RST_COMP BIT(13)
224#define INTR__PIPE_CMD_ERR BIT(14)
225#define INTR__PAGE_XFER_INC BIT(15)
226#define INTR__ERASED_PAGE BIT(16)
227
228#define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
229#define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
230#define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
231
232#define ECC_THRESHOLD 0x600
233#define ECC_THRESHOLD__VALUE GENMASK(9, 0)
234
235#define ECC_ERROR_BLOCK_ADDRESS 0x610
236#define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
237
238#define ECC_ERROR_PAGE_ADDRESS 0x620
239#define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
240#define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)
241
242#define ECC_ERROR_ADDRESS 0x630
243#define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
244#define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12)
245
246#define ERR_CORRECTION_INFO 0x640
247#define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0)
248#define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8)
249#define ERR_CORRECTION_INFO__UNCOR BIT(14)
250#define ERR_CORRECTION_INFO__LAST_ERR BIT(15)
251
252#define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
253#define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
254#define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
255#define ECC_COR_INFO__UNCOR_ERR BIT(7)
256
257#define CFG_DATA_BLOCK_SIZE 0x6b0
258
259#define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
260
261#define CFG_NUM_DATA_BLOCKS 0x6d0
262
263#define CFG_META_DATA_SIZE 0x6e0
264
265#define DMA_ENABLE 0x700
266#define DMA_ENABLE__FLAG BIT(0)
267
268#define IGNORE_ECC_DONE 0x710
269#define IGNORE_ECC_DONE__FLAG BIT(0)
270
271#define DMA_INTR 0x720
272#define DMA_INTR_EN 0x730
273#define DMA_INTR__TARGET_ERROR BIT(0)
274#define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
275#define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
276#define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
277#define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
278#define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
279
280#define TARGET_ERR_ADDR_LO 0x740
281#define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
282
283#define TARGET_ERR_ADDR_HI 0x750
284#define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
285
286#define CHNL_ACTIVE 0x760
287#define CHNL_ACTIVE__CHANNEL0 BIT(0)
288#define CHNL_ACTIVE__CHANNEL1 BIT(1)
289#define CHNL_ACTIVE__CHANNEL2 BIT(2)
290#define CHNL_ACTIVE__CHANNEL3 BIT(3)
291
292struct udevice;
293
294struct denali_nand_info {
295 struct nand_chip nand;
296 unsigned long clk_rate;
297 unsigned long clk_x_rate;
298 int active_bank;
299 struct udevice *dev;
300 uint32_t page;
301 void __iomem *reg;
302 void __iomem *host;
303 u32 irq_mask;
304 u32 irq_status;
305 int irq;
306 void *buf;
307 dma_addr_t dma_addr;
308 int dma_avail;
309 int devs_per_cs;
310 int oob_skip_bytes;
311 int max_banks;
312 unsigned int revision;
313 unsigned int caps;
314 const struct nand_ecc_caps *ecc_caps;
315 u32 (*host_read)(struct denali_nand_info *denali, u32 addr);
316 void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
317 void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
318 int page, int write);
319 struct reset_ctl_bulk resets;
320};
321
322#define DENALI_CAP_HW_ECC_FIXUP BIT(0)
323#define DENALI_CAP_DMA_64BIT BIT(1)
324
325int denali_calc_ecc_bytes(int step_size, int strength);
326int denali_init(struct denali_nand_info *denali);
327
328#endif
329