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5#include <common.h>
6#include <clk.h>
7#include <dm.h>
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31#include <net.h>
32#ifndef CONFIG_DM_ETH
33#include <netdev.h>
34#endif
35#include <malloc.h>
36#include <miiphy.h>
37
38#include <linux/mii.h>
39#include <asm/io.h>
40#include <asm/dma-mapping.h>
41#include <asm/arch/clk.h>
42#include <linux/errno.h>
43
44#include "macb.h"
45
46DECLARE_GLOBAL_DATA_PTR;
47
48#define MACB_RX_BUFFER_SIZE 4096
49#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
50#define MACB_TX_RING_SIZE 16
51#define MACB_TX_TIMEOUT 1000
52#define MACB_AUTONEG_TIMEOUT 5000000
53
54#ifdef CONFIG_MACB_ZYNQ
55
56#define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
57
58#define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
59
60#define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
61
62#define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
63#define MACB_ZYNQ_GEM_DMACR_INIT \
64 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
65 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
66 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
67 MACB_ZYNQ_GEM_DMACR_RXBUF)
68#endif
69
70struct macb_dma_desc {
71 u32 addr;
72 u32 ctrl;
73};
74
75#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
76#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
77#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
78#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
79
80#define RXADDR_USED 0x00000001
81#define RXADDR_WRAP 0x00000002
82
83#define RXBUF_FRMLEN_MASK 0x00000fff
84#define RXBUF_FRAME_START 0x00004000
85#define RXBUF_FRAME_END 0x00008000
86#define RXBUF_TYPEID_MATCH 0x00400000
87#define RXBUF_ADDR4_MATCH 0x00800000
88#define RXBUF_ADDR3_MATCH 0x01000000
89#define RXBUF_ADDR2_MATCH 0x02000000
90#define RXBUF_ADDR1_MATCH 0x04000000
91#define RXBUF_BROADCAST 0x80000000
92
93#define TXBUF_FRMLEN_MASK 0x000007ff
94#define TXBUF_FRAME_END 0x00008000
95#define TXBUF_NOCRC 0x00010000
96#define TXBUF_EXHAUSTED 0x08000000
97#define TXBUF_UNDERRUN 0x10000000
98#define TXBUF_MAXRETRY 0x20000000
99#define TXBUF_WRAP 0x40000000
100#define TXBUF_USED 0x80000000
101
102struct macb_device {
103 void *regs;
104
105 unsigned int rx_tail;
106 unsigned int tx_head;
107 unsigned int tx_tail;
108 unsigned int next_rx_tail;
109 bool wrapped;
110
111 void *rx_buffer;
112 void *tx_buffer;
113 struct macb_dma_desc *rx_ring;
114 struct macb_dma_desc *tx_ring;
115
116 unsigned long rx_buffer_dma;
117 unsigned long rx_ring_dma;
118 unsigned long tx_ring_dma;
119
120 struct macb_dma_desc *dummy_desc;
121 unsigned long dummy_desc_dma;
122
123 const struct device *dev;
124#ifndef CONFIG_DM_ETH
125 struct eth_device netdev;
126#endif
127 unsigned short phy_addr;
128 struct mii_dev *bus;
129#ifdef CONFIG_PHYLIB
130 struct phy_device *phydev;
131#endif
132
133#ifdef CONFIG_DM_ETH
134#ifdef CONFIG_CLK
135 unsigned long pclk_rate;
136#endif
137 phy_interface_t phy_interface;
138#endif
139};
140#ifndef CONFIG_DM_ETH
141#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
142#endif
143
144static int macb_is_gem(struct macb_device *macb)
145{
146 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
147}
148
149#ifndef cpu_is_sama5d2
150#define cpu_is_sama5d2() 0
151#endif
152
153#ifndef cpu_is_sama5d4
154#define cpu_is_sama5d4() 0
155#endif
156
157static int gem_is_gigabit_capable(struct macb_device *macb)
158{
159
160
161
162
163 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
164}
165
166static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
167{
168 unsigned long netctl;
169 unsigned long netstat;
170 unsigned long frame;
171
172 netctl = macb_readl(macb, NCR);
173 netctl |= MACB_BIT(MPE);
174 macb_writel(macb, NCR, netctl);
175
176 frame = (MACB_BF(SOF, 1)
177 | MACB_BF(RW, 1)
178 | MACB_BF(PHYA, macb->phy_addr)
179 | MACB_BF(REGA, reg)
180 | MACB_BF(CODE, 2)
181 | MACB_BF(DATA, value));
182 macb_writel(macb, MAN, frame);
183
184 do {
185 netstat = macb_readl(macb, NSR);
186 } while (!(netstat & MACB_BIT(IDLE)));
187
188 netctl = macb_readl(macb, NCR);
189 netctl &= ~MACB_BIT(MPE);
190 macb_writel(macb, NCR, netctl);
191}
192
193static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
194{
195 unsigned long netctl;
196 unsigned long netstat;
197 unsigned long frame;
198
199 netctl = macb_readl(macb, NCR);
200 netctl |= MACB_BIT(MPE);
201 macb_writel(macb, NCR, netctl);
202
203 frame = (MACB_BF(SOF, 1)
204 | MACB_BF(RW, 2)
205 | MACB_BF(PHYA, macb->phy_addr)
206 | MACB_BF(REGA, reg)
207 | MACB_BF(CODE, 2));
208 macb_writel(macb, MAN, frame);
209
210 do {
211 netstat = macb_readl(macb, NSR);
212 } while (!(netstat & MACB_BIT(IDLE)));
213
214 frame = macb_readl(macb, MAN);
215
216 netctl = macb_readl(macb, NCR);
217 netctl &= ~MACB_BIT(MPE);
218 macb_writel(macb, NCR, netctl);
219
220 return MACB_BFEXT(DATA, frame);
221}
222
223void __weak arch_get_mdio_control(const char *name)
224{
225 return;
226}
227
228#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
229
230int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
231{
232 u16 value = 0;
233#ifdef CONFIG_DM_ETH
234 struct udevice *dev = eth_get_dev_by_name(bus->name);
235 struct macb_device *macb = dev_get_priv(dev);
236#else
237 struct eth_device *dev = eth_get_dev_by_name(bus->name);
238 struct macb_device *macb = to_macb(dev);
239#endif
240
241 if (macb->phy_addr != phy_adr)
242 return -1;
243
244 arch_get_mdio_control(bus->name);
245 value = macb_mdio_read(macb, reg);
246
247 return value;
248}
249
250int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
251 u16 value)
252{
253#ifdef CONFIG_DM_ETH
254 struct udevice *dev = eth_get_dev_by_name(bus->name);
255 struct macb_device *macb = dev_get_priv(dev);
256#else
257 struct eth_device *dev = eth_get_dev_by_name(bus->name);
258 struct macb_device *macb = to_macb(dev);
259#endif
260
261 if (macb->phy_addr != phy_adr)
262 return -1;
263
264 arch_get_mdio_control(bus->name);
265 macb_mdio_write(macb, reg, value);
266
267 return 0;
268}
269#endif
270
271#define RX 1
272#define TX 0
273static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
274{
275 if (rx)
276 invalidate_dcache_range(macb->rx_ring_dma,
277 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
278 PKTALIGN));
279 else
280 invalidate_dcache_range(macb->tx_ring_dma,
281 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
282 PKTALIGN));
283}
284
285static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
286{
287 if (rx)
288 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
289 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
290 else
291 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
292 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
293}
294
295static inline void macb_flush_rx_buffer(struct macb_device *macb)
296{
297 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
298 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
299}
300
301static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
302{
303 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
304 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
305}
306
307#if defined(CONFIG_CMD_NET)
308
309static int _macb_send(struct macb_device *macb, const char *name, void *packet,
310 int length)
311{
312 unsigned long paddr, ctrl;
313 unsigned int tx_head = macb->tx_head;
314 int i;
315
316 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
317
318 ctrl = length & TXBUF_FRMLEN_MASK;
319 ctrl |= TXBUF_FRAME_END;
320 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
321 ctrl |= TXBUF_WRAP;
322 macb->tx_head = 0;
323 } else {
324 macb->tx_head++;
325 }
326
327 macb->tx_ring[tx_head].ctrl = ctrl;
328 macb->tx_ring[tx_head].addr = paddr;
329 barrier();
330 macb_flush_ring_desc(macb, TX);
331
332 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
333 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
334
335
336
337
338
339 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
340 barrier();
341 macb_invalidate_ring_desc(macb, TX);
342 ctrl = macb->tx_ring[tx_head].ctrl;
343 if (ctrl & TXBUF_USED)
344 break;
345 udelay(1);
346 }
347
348 dma_unmap_single(packet, length, paddr);
349
350 if (i <= MACB_TX_TIMEOUT) {
351 if (ctrl & TXBUF_UNDERRUN)
352 printf("%s: TX underrun\n", name);
353 if (ctrl & TXBUF_EXHAUSTED)
354 printf("%s: TX buffers exhausted in mid frame\n", name);
355 } else {
356 printf("%s: TX timeout\n", name);
357 }
358
359
360 return 0;
361}
362
363static void reclaim_rx_buffers(struct macb_device *macb,
364 unsigned int new_tail)
365{
366 unsigned int i;
367
368 i = macb->rx_tail;
369
370 macb_invalidate_ring_desc(macb, RX);
371 while (i > new_tail) {
372 macb->rx_ring[i].addr &= ~RXADDR_USED;
373 i++;
374 if (i > MACB_RX_RING_SIZE)
375 i = 0;
376 }
377
378 while (i < new_tail) {
379 macb->rx_ring[i].addr &= ~RXADDR_USED;
380 i++;
381 }
382
383 barrier();
384 macb_flush_ring_desc(macb, RX);
385 macb->rx_tail = new_tail;
386}
387
388static int _macb_recv(struct macb_device *macb, uchar **packetp)
389{
390 unsigned int next_rx_tail = macb->next_rx_tail;
391 void *buffer;
392 int length;
393 u32 status;
394
395 macb->wrapped = false;
396 for (;;) {
397 macb_invalidate_ring_desc(macb, RX);
398
399 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
400 return -EAGAIN;
401
402 status = macb->rx_ring[next_rx_tail].ctrl;
403 if (status & RXBUF_FRAME_START) {
404 if (next_rx_tail != macb->rx_tail)
405 reclaim_rx_buffers(macb, next_rx_tail);
406 macb->wrapped = false;
407 }
408
409 if (status & RXBUF_FRAME_END) {
410 buffer = macb->rx_buffer + 128 * macb->rx_tail;
411 length = status & RXBUF_FRMLEN_MASK;
412
413 macb_invalidate_rx_buffer(macb);
414 if (macb->wrapped) {
415 unsigned int headlen, taillen;
416
417 headlen = 128 * (MACB_RX_RING_SIZE
418 - macb->rx_tail);
419 taillen = length - headlen;
420 memcpy((void *)net_rx_packets[0],
421 buffer, headlen);
422 memcpy((void *)net_rx_packets[0] + headlen,
423 macb->rx_buffer, taillen);
424 *packetp = (void *)net_rx_packets[0];
425 } else {
426 *packetp = buffer;
427 }
428
429 if (++next_rx_tail >= MACB_RX_RING_SIZE)
430 next_rx_tail = 0;
431 macb->next_rx_tail = next_rx_tail;
432 return length;
433 } else {
434 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
435 macb->wrapped = true;
436 next_rx_tail = 0;
437 }
438 }
439 barrier();
440 }
441}
442
443static void macb_phy_reset(struct macb_device *macb, const char *name)
444{
445 int i;
446 u16 status, adv;
447
448 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
449 macb_mdio_write(macb, MII_ADVERTISE, adv);
450 printf("%s: Starting autonegotiation...\n", name);
451 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
452 | BMCR_ANRESTART));
453
454 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
455 status = macb_mdio_read(macb, MII_BMSR);
456 if (status & BMSR_ANEGCOMPLETE)
457 break;
458 udelay(100);
459 }
460
461 if (status & BMSR_ANEGCOMPLETE)
462 printf("%s: Autonegotiation complete\n", name);
463 else
464 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
465 name, status);
466}
467
468static int macb_phy_find(struct macb_device *macb, const char *name)
469{
470 int i;
471 u16 phy_id;
472
473
474 for (i = 0; i < 32; i++) {
475 macb->phy_addr = i;
476 phy_id = macb_mdio_read(macb, MII_PHYSID1);
477 if (phy_id != 0xffff) {
478 printf("%s: PHY present at %d\n", name, i);
479 return 0;
480 }
481 }
482
483
484 printf("%s: PHY not found\n", name);
485
486 return -ENODEV;
487}
488
489
490
491
492
493
494
495
496
497#ifdef CONFIG_DM_ETH
498int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
499{
500#ifdef CONFIG_CLK
501 struct clk tx_clk;
502 ulong rate;
503 int ret;
504
505
506
507
508
509 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
510 if (ret)
511 return 0;
512
513 switch (speed) {
514 case _10BASET:
515 rate = 2500000;
516 break;
517 case _100BASET:
518 rate = 25000000;
519 break;
520 case _1000BASET:
521 rate = 125000000;
522 break;
523 default:
524
525 return 0;
526 }
527
528 if (tx_clk.dev) {
529 ret = clk_set_rate(&tx_clk, rate);
530 if (ret)
531 return ret;
532 }
533#endif
534
535 return 0;
536}
537#else
538int __weak macb_linkspd_cb(void *regs, unsigned int speed)
539{
540 return 0;
541}
542#endif
543
544#ifdef CONFIG_DM_ETH
545static int macb_phy_init(struct udevice *dev, const char *name)
546#else
547static int macb_phy_init(struct macb_device *macb, const char *name)
548#endif
549{
550#ifdef CONFIG_DM_ETH
551 struct macb_device *macb = dev_get_priv(dev);
552#endif
553 u32 ncfgr;
554 u16 phy_id, status, adv, lpa;
555 int media, speed, duplex;
556 int ret;
557 int i;
558
559 arch_get_mdio_control(name);
560
561 ret = macb_phy_find(macb, name);
562 if (ret)
563 return ret;
564
565
566 phy_id = macb_mdio_read(macb, MII_PHYSID1);
567 if (phy_id == 0xffff) {
568 printf("%s: No PHY present\n", name);
569 return -ENODEV;
570 }
571
572#ifdef CONFIG_PHYLIB
573#ifdef CONFIG_DM_ETH
574 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
575 macb->phy_interface);
576#else
577
578 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
579 PHY_INTERFACE_MODE_RGMII);
580#endif
581 if (!macb->phydev) {
582 printf("phy_connect failed\n");
583 return -ENODEV;
584 }
585
586 phy_config(macb->phydev);
587#endif
588
589 status = macb_mdio_read(macb, MII_BMSR);
590 if (!(status & BMSR_LSTATUS)) {
591
592 macb_phy_reset(macb, name);
593
594 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
595 status = macb_mdio_read(macb, MII_BMSR);
596 if (status & BMSR_LSTATUS) {
597
598
599
600
601 mdelay(10);
602 break;
603 }
604 udelay(100);
605 }
606 }
607
608 if (!(status & BMSR_LSTATUS)) {
609 printf("%s: link down (status: 0x%04x)\n",
610 name, status);
611 return -ENETDOWN;
612 }
613
614
615 if (gem_is_gigabit_capable(macb)) {
616 lpa = macb_mdio_read(macb, MII_STAT1000);
617
618 if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
619 duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
620
621 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
622 name,
623 duplex ? "full" : "half",
624 lpa);
625
626 ncfgr = macb_readl(macb, NCFGR);
627 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
628 ncfgr |= GEM_BIT(GBE);
629
630 if (duplex)
631 ncfgr |= MACB_BIT(FD);
632
633 macb_writel(macb, NCFGR, ncfgr);
634
635#ifdef CONFIG_DM_ETH
636 ret = macb_linkspd_cb(dev, _1000BASET);
637#else
638 ret = macb_linkspd_cb(macb->regs, _1000BASET);
639#endif
640 if (ret)
641 return ret;
642
643 return 0;
644 }
645 }
646
647
648 adv = macb_mdio_read(macb, MII_ADVERTISE);
649 lpa = macb_mdio_read(macb, MII_LPA);
650 media = mii_nway_result(lpa & adv);
651 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
652 ? 1 : 0);
653 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
654 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
655 name,
656 speed ? "100" : "10",
657 duplex ? "full" : "half",
658 lpa);
659
660 ncfgr = macb_readl(macb, NCFGR);
661 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
662 if (speed) {
663 ncfgr |= MACB_BIT(SPD);
664#ifdef CONFIG_DM_ETH
665 ret = macb_linkspd_cb(dev, _100BASET);
666#else
667 ret = macb_linkspd_cb(macb->regs, _100BASET);
668#endif
669 } else {
670#ifdef CONFIG_DM_ETH
671 ret = macb_linkspd_cb(dev, _10BASET);
672#else
673 ret = macb_linkspd_cb(macb->regs, _10BASET);
674#endif
675 }
676
677 if (ret)
678 return ret;
679
680 if (duplex)
681 ncfgr |= MACB_BIT(FD);
682 macb_writel(macb, NCFGR, ncfgr);
683
684 return 0;
685}
686
687static int gmac_init_multi_queues(struct macb_device *macb)
688{
689 int i, num_queues = 1;
690 u32 queue_mask;
691
692
693 queue_mask = gem_readl(macb, DCFG6) & 0xff;
694 queue_mask |= 0x1;
695
696 for (i = 1; i < MACB_MAX_QUEUES; i++)
697 if (queue_mask & (1 << i))
698 num_queues++;
699
700 macb->dummy_desc->ctrl = TXBUF_USED;
701 macb->dummy_desc->addr = 0;
702 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
703 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
704
705 for (i = 1; i < num_queues; i++)
706 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
707
708 return 0;
709}
710
711#ifdef CONFIG_DM_ETH
712static int _macb_init(struct udevice *dev, const char *name)
713#else
714static int _macb_init(struct macb_device *macb, const char *name)
715#endif
716{
717#ifdef CONFIG_DM_ETH
718 struct macb_device *macb = dev_get_priv(dev);
719#endif
720 unsigned long paddr;
721 int ret;
722 int i;
723
724
725
726
727
728
729
730 paddr = macb->rx_buffer_dma;
731 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
732 if (i == (MACB_RX_RING_SIZE - 1))
733 paddr |= RXADDR_WRAP;
734 macb->rx_ring[i].addr = paddr;
735 macb->rx_ring[i].ctrl = 0;
736 paddr += 128;
737 }
738 macb_flush_ring_desc(macb, RX);
739 macb_flush_rx_buffer(macb);
740
741 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
742 macb->tx_ring[i].addr = 0;
743 if (i == (MACB_TX_RING_SIZE - 1))
744 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
745 else
746 macb->tx_ring[i].ctrl = TXBUF_USED;
747 }
748 macb_flush_ring_desc(macb, TX);
749
750 macb->rx_tail = 0;
751 macb->tx_head = 0;
752 macb->tx_tail = 0;
753 macb->next_rx_tail = 0;
754
755#ifdef CONFIG_MACB_ZYNQ
756 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
757#endif
758
759 macb_writel(macb, RBQP, macb->rx_ring_dma);
760 macb_writel(macb, TBQP, macb->tx_ring_dma);
761
762 if (macb_is_gem(macb)) {
763
764 gmac_init_multi_queues(macb);
765
766
767
768
769
770
771
772#ifdef CONFIG_DM_ETH
773 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
774 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
775 gem_writel(macb, UR, GEM_BIT(RGMII));
776 else
777 gem_writel(macb, UR, 0);
778#else
779#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
780 gem_writel(macb, UR, GEM_BIT(RGMII));
781#else
782 gem_writel(macb, UR, 0);
783#endif
784#endif
785 } else {
786
787#ifdef CONFIG_DM_ETH
788#ifdef CONFIG_AT91FAMILY
789 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
790 macb_writel(macb, USRIO,
791 MACB_BIT(RMII) | MACB_BIT(CLKEN));
792 } else {
793 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
794 }
795#else
796 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
797 macb_writel(macb, USRIO, 0);
798 else
799 macb_writel(macb, USRIO, MACB_BIT(MII));
800#endif
801#else
802#ifdef CONFIG_RMII
803#ifdef CONFIG_AT91FAMILY
804 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
805#else
806 macb_writel(macb, USRIO, 0);
807#endif
808#else
809#ifdef CONFIG_AT91FAMILY
810 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
811#else
812 macb_writel(macb, USRIO, MACB_BIT(MII));
813#endif
814#endif
815#endif
816 }
817
818#ifdef CONFIG_DM_ETH
819 ret = macb_phy_init(dev, name);
820#else
821 ret = macb_phy_init(macb, name);
822#endif
823 if (ret)
824 return ret;
825
826
827 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
828
829 return 0;
830}
831
832static void _macb_halt(struct macb_device *macb)
833{
834 u32 ncr, tsr;
835
836
837 ncr = macb_readl(macb, NCR);
838 ncr |= MACB_BIT(THALT);
839 macb_writel(macb, NCR, ncr);
840
841 do {
842 tsr = macb_readl(macb, TSR);
843 } while (tsr & MACB_BIT(TGO));
844
845
846 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
847}
848
849static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
850{
851 u32 hwaddr_bottom;
852 u16 hwaddr_top;
853
854
855 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
856 enetaddr[2] << 16 | enetaddr[3] << 24;
857 macb_writel(macb, SA1B, hwaddr_bottom);
858 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
859 macb_writel(macb, SA1T, hwaddr_top);
860 return 0;
861}
862
863static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
864{
865 u32 config;
866#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
867 unsigned long macb_hz = macb->pclk_rate;
868#else
869 unsigned long macb_hz = get_macb_pclk_rate(id);
870#endif
871
872 if (macb_hz < 20000000)
873 config = MACB_BF(CLK, MACB_CLK_DIV8);
874 else if (macb_hz < 40000000)
875 config = MACB_BF(CLK, MACB_CLK_DIV16);
876 else if (macb_hz < 80000000)
877 config = MACB_BF(CLK, MACB_CLK_DIV32);
878 else
879 config = MACB_BF(CLK, MACB_CLK_DIV64);
880
881 return config;
882}
883
884static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
885{
886 u32 config;
887
888#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
889 unsigned long macb_hz = macb->pclk_rate;
890#else
891 unsigned long macb_hz = get_macb_pclk_rate(id);
892#endif
893
894 if (macb_hz < 20000000)
895 config = GEM_BF(CLK, GEM_CLK_DIV8);
896 else if (macb_hz < 40000000)
897 config = GEM_BF(CLK, GEM_CLK_DIV16);
898 else if (macb_hz < 80000000)
899 config = GEM_BF(CLK, GEM_CLK_DIV32);
900 else if (macb_hz < 120000000)
901 config = GEM_BF(CLK, GEM_CLK_DIV48);
902 else if (macb_hz < 160000000)
903 config = GEM_BF(CLK, GEM_CLK_DIV64);
904 else
905 config = GEM_BF(CLK, GEM_CLK_DIV96);
906
907 return config;
908}
909
910
911
912
913
914
915static u32 macb_dbw(struct macb_device *macb)
916{
917 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
918 case 4:
919 return GEM_BF(DBW, GEM_DBW128);
920 case 2:
921 return GEM_BF(DBW, GEM_DBW64);
922 case 1:
923 default:
924 return GEM_BF(DBW, GEM_DBW32);
925 }
926}
927
928static void _macb_eth_initialize(struct macb_device *macb)
929{
930 int id = 0;
931 u32 ncfgr;
932
933
934 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
935 &macb->rx_buffer_dma);
936 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
937 &macb->rx_ring_dma);
938 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
939 &macb->tx_ring_dma);
940 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
941 &macb->dummy_desc_dma);
942
943
944
945
946
947 if (macb_is_gem(macb)) {
948 ncfgr = gem_mdc_clk_div(id, macb);
949 ncfgr |= macb_dbw(macb);
950 } else {
951 ncfgr = macb_mdc_clk_div(id, macb);
952 }
953
954 macb_writel(macb, NCFGR, ncfgr);
955}
956
957#ifndef CONFIG_DM_ETH
958static int macb_send(struct eth_device *netdev, void *packet, int length)
959{
960 struct macb_device *macb = to_macb(netdev);
961
962 return _macb_send(macb, netdev->name, packet, length);
963}
964
965static int macb_recv(struct eth_device *netdev)
966{
967 struct macb_device *macb = to_macb(netdev);
968 uchar *packet;
969 int length;
970
971 macb->wrapped = false;
972 for (;;) {
973 macb->next_rx_tail = macb->rx_tail;
974 length = _macb_recv(macb, &packet);
975 if (length >= 0) {
976 net_process_received_packet(packet, length);
977 reclaim_rx_buffers(macb, macb->next_rx_tail);
978 } else {
979 return length;
980 }
981 }
982}
983
984static int macb_init(struct eth_device *netdev, bd_t *bd)
985{
986 struct macb_device *macb = to_macb(netdev);
987
988 return _macb_init(macb, netdev->name);
989}
990
991static void macb_halt(struct eth_device *netdev)
992{
993 struct macb_device *macb = to_macb(netdev);
994
995 return _macb_halt(macb);
996}
997
998static int macb_write_hwaddr(struct eth_device *netdev)
999{
1000 struct macb_device *macb = to_macb(netdev);
1001
1002 return _macb_write_hwaddr(macb, netdev->enetaddr);
1003}
1004
1005int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1006{
1007 struct macb_device *macb;
1008 struct eth_device *netdev;
1009
1010 macb = malloc(sizeof(struct macb_device));
1011 if (!macb) {
1012 printf("Error: Failed to allocate memory for MACB%d\n", id);
1013 return -1;
1014 }
1015 memset(macb, 0, sizeof(struct macb_device));
1016
1017 netdev = &macb->netdev;
1018
1019 macb->regs = regs;
1020 macb->phy_addr = phy_addr;
1021
1022 if (macb_is_gem(macb))
1023 sprintf(netdev->name, "gmac%d", id);
1024 else
1025 sprintf(netdev->name, "macb%d", id);
1026
1027 netdev->init = macb_init;
1028 netdev->halt = macb_halt;
1029 netdev->send = macb_send;
1030 netdev->recv = macb_recv;
1031 netdev->write_hwaddr = macb_write_hwaddr;
1032
1033 _macb_eth_initialize(macb);
1034
1035 eth_register(netdev);
1036
1037#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1038 int retval;
1039 struct mii_dev *mdiodev = mdio_alloc();
1040 if (!mdiodev)
1041 return -ENOMEM;
1042 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1043 mdiodev->read = macb_miiphy_read;
1044 mdiodev->write = macb_miiphy_write;
1045
1046 retval = mdio_register(mdiodev);
1047 if (retval < 0)
1048 return retval;
1049 macb->bus = miiphy_get_dev_by_name(netdev->name);
1050#endif
1051 return 0;
1052}
1053#endif
1054
1055#ifdef CONFIG_DM_ETH
1056
1057static int macb_start(struct udevice *dev)
1058{
1059 return _macb_init(dev, dev->name);
1060}
1061
1062static int macb_send(struct udevice *dev, void *packet, int length)
1063{
1064 struct macb_device *macb = dev_get_priv(dev);
1065
1066 return _macb_send(macb, dev->name, packet, length);
1067}
1068
1069static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1070{
1071 struct macb_device *macb = dev_get_priv(dev);
1072
1073 macb->next_rx_tail = macb->rx_tail;
1074 macb->wrapped = false;
1075
1076 return _macb_recv(macb, packetp);
1077}
1078
1079static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1080{
1081 struct macb_device *macb = dev_get_priv(dev);
1082
1083 reclaim_rx_buffers(macb, macb->next_rx_tail);
1084
1085 return 0;
1086}
1087
1088static void macb_stop(struct udevice *dev)
1089{
1090 struct macb_device *macb = dev_get_priv(dev);
1091
1092 _macb_halt(macb);
1093}
1094
1095static int macb_write_hwaddr(struct udevice *dev)
1096{
1097 struct eth_pdata *plat = dev_get_platdata(dev);
1098 struct macb_device *macb = dev_get_priv(dev);
1099
1100 return _macb_write_hwaddr(macb, plat->enetaddr);
1101}
1102
1103static const struct eth_ops macb_eth_ops = {
1104 .start = macb_start,
1105 .send = macb_send,
1106 .recv = macb_recv,
1107 .stop = macb_stop,
1108 .free_pkt = macb_free_pkt,
1109 .write_hwaddr = macb_write_hwaddr,
1110};
1111
1112#ifdef CONFIG_CLK
1113static int macb_enable_clk(struct udevice *dev)
1114{
1115 struct macb_device *macb = dev_get_priv(dev);
1116 struct clk clk;
1117 ulong clk_rate;
1118 int ret;
1119
1120 ret = clk_get_by_index(dev, 0, &clk);
1121 if (ret)
1122 return -EINVAL;
1123
1124
1125
1126
1127
1128
1129 ret = clk_enable(&clk);
1130 if (ret && ret != -ENOSYS)
1131 return ret;
1132
1133 clk_rate = clk_get_rate(&clk);
1134 if (!clk_rate)
1135 return -EINVAL;
1136
1137 macb->pclk_rate = clk_rate;
1138
1139 return 0;
1140}
1141#endif
1142
1143static int macb_eth_probe(struct udevice *dev)
1144{
1145 struct eth_pdata *pdata = dev_get_platdata(dev);
1146 struct macb_device *macb = dev_get_priv(dev);
1147 const char *phy_mode;
1148 __maybe_unused int ret;
1149
1150 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1151 NULL);
1152 if (phy_mode)
1153 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1154 if (macb->phy_interface == -1) {
1155 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1156 return -EINVAL;
1157 }
1158
1159 macb->regs = (void *)pdata->iobase;
1160
1161#ifdef CONFIG_CLK
1162 ret = macb_enable_clk(dev);
1163 if (ret)
1164 return ret;
1165#endif
1166
1167 _macb_eth_initialize(macb);
1168
1169#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1170 macb->bus = mdio_alloc();
1171 if (!macb->bus)
1172 return -ENOMEM;
1173 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1174 macb->bus->read = macb_miiphy_read;
1175 macb->bus->write = macb_miiphy_write;
1176
1177 ret = mdio_register(macb->bus);
1178 if (ret < 0)
1179 return ret;
1180 macb->bus = miiphy_get_dev_by_name(dev->name);
1181#endif
1182
1183 return 0;
1184}
1185
1186static int macb_eth_remove(struct udevice *dev)
1187{
1188 struct macb_device *macb = dev_get_priv(dev);
1189
1190#ifdef CONFIG_PHYLIB
1191 free(macb->phydev);
1192#endif
1193 mdio_unregister(macb->bus);
1194 mdio_free(macb->bus);
1195
1196 return 0;
1197}
1198
1199
1200
1201
1202
1203
1204
1205int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1206{
1207 return 0;
1208}
1209
1210static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1211{
1212 struct eth_pdata *pdata = dev_get_platdata(dev);
1213
1214 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1215 if (!pdata->iobase)
1216 return -EINVAL;
1217
1218 return macb_late_eth_ofdata_to_platdata(dev);
1219}
1220
1221static const struct udevice_id macb_eth_ids[] = {
1222 { .compatible = "cdns,macb" },
1223 { .compatible = "cdns,at91sam9260-macb" },
1224 { .compatible = "atmel,sama5d2-gem" },
1225 { .compatible = "atmel,sama5d3-gem" },
1226 { .compatible = "atmel,sama5d4-gem" },
1227 { .compatible = "cdns,zynq-gem" },
1228 { }
1229};
1230
1231U_BOOT_DRIVER(eth_macb) = {
1232 .name = "eth_macb",
1233 .id = UCLASS_ETH,
1234 .of_match = macb_eth_ids,
1235 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1236 .probe = macb_eth_probe,
1237 .remove = macb_eth_remove,
1238 .ops = &macb_eth_ops,
1239 .priv_auto_alloc_size = sizeof(struct macb_device),
1240 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1241};
1242#endif
1243
1244#endif
1245