LXR uboot/drivers/net/phy/broadcom.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Broadcom PHY drivers
   4 *
   5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
   6 * author Andy Fleming
   7 */
   8#include <common.h>
   9#include <phy.h>
  10
  11/* Broadcom BCM54xx -- taken from linux sungem_phy */
  12#define MIIM_BCM54xx_AUXCNTL                    0x18
  13#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7))
  14#define MIIM_BCM54xx_AUXSTATUS                  0x19
  15#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK    0x0700
  16#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT   8
  17
  18#define MIIM_BCM54XX_SHD                        0x1c
  19#define MIIM_BCM54XX_SHD_WRITE                  0x8000
  20#define MIIM_BCM54XX_SHD_VAL(x)                 ((x & 0x1f) << 10)
  21#define MIIM_BCM54XX_SHD_DATA(x)                ((x & 0x3ff) << 0)
  22#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data)   \
  23        (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
  24         MIIM_BCM54XX_SHD_DATA(data))
  25
  26#define MIIM_BCM54XX_EXP_DATA           0x15    /* Expansion register data */
  27#define MIIM_BCM54XX_EXP_SEL            0x17    /* Expansion register select */
  28#define MIIM_BCM54XX_EXP_SEL_SSD        0x0e00  /* Secondary SerDes select */
  29#define MIIM_BCM54XX_EXP_SEL_ER         0x0f00  /* Expansion register select */
  30
  31#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC   0x0007
  32#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN  0x0800
  33
  34#define MIIM_BCM_CHANNEL_WIDTH    0x2000
  35
  36static void bcm_phy_write_misc(struct phy_device *phydev,
  37                               u16 reg, u16 chl, u16 value)
  38{
  39        int reg_val;
  40
  41        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
  42                  MIIM_BCM_AUXCNTL_SHDWSEL_MISC);
  43
  44        reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL);
  45        reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN;
  46        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val);
  47
  48        reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg;
  49        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val);
  50
  51        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value);
  52}
  53
  54/* Broadcom BCM5461S */
  55static int bcm5461_config(struct phy_device *phydev)
  56{
  57        genphy_config_aneg(phydev);
  58
  59        phy_reset(phydev);
  60
  61        return 0;
  62}
  63
  64static int bcm54xx_parse_status(struct phy_device *phydev)
  65{
  66        unsigned int mii_reg;
  67
  68        mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS);
  69
  70        switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
  71                        MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
  72        case 1:
  73                phydev->duplex = DUPLEX_HALF;
  74                phydev->speed = SPEED_10;
  75                break;
  76        case 2:
  77                phydev->duplex = DUPLEX_FULL;
  78                phydev->speed = SPEED_10;
  79                break;
  80        case 3:
  81                phydev->duplex = DUPLEX_HALF;
  82                phydev->speed = SPEED_100;
  83                break;
  84        case 5:
  85                phydev->duplex = DUPLEX_FULL;
  86                phydev->speed = SPEED_100;
  87                break;
  88        case 6:
  89                phydev->duplex = DUPLEX_HALF;
  90                phydev->speed = SPEED_1000;
  91                break;
  92        case 7:
  93                phydev->duplex = DUPLEX_FULL;
  94                phydev->speed = SPEED_1000;
  95                break;
  96        default:
  97                printf("Auto-neg error, defaulting to 10BT/HD\n");
  98                phydev->duplex = DUPLEX_HALF;
  99                phydev->speed = SPEED_10;
 100                break;
 101        }
 102
 103        return 0;
 104}
 105
 106static int bcm54xx_startup(struct phy_device *phydev)
 107{
 108        int ret;
 109
 110        /* Read the Status (2x to make sure link is right) */
 111        ret = genphy_update_link(phydev);
 112        if (ret)
 113                return ret;
 114
 115        return bcm54xx_parse_status(phydev);
 116}
 117
 118/* Broadcom BCM5482S */
 119/*
 120 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
 121 * circumstances.  eg a gigabit TSEC connected to a gigabit switch with
 122 * a 4-wire ethernet cable.  Both ends advertise gigabit, but can't
 123 * link.  "Ethernet@Wirespeed" reduces advertised speed until link
 124 * can be achieved.
 125 */
 126static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg)
 127{
 128        return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010;
 129}
 130
 131static int bcm5482_config(struct phy_device *phydev)
 132{
 133        unsigned int reg;
 134
 135        /* reset the PHY */
 136        reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
 137        reg |= BMCR_RESET;
 138        phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
 139
 140        /* Setup read from auxilary control shadow register 7 */
 141        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
 142                        MIIM_BCM54xx_AUXCNTL_ENCODE(7));
 143        /* Read Misc Control register and or in Ethernet@Wirespeed */
 144        reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL);
 145        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg);
 146
 147        /* Initial config/enable of secondary SerDes interface */
 148        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
 149                        MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf));
 150        /* Write intial value to secondary SerDes Contol */
 151        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
 152                        MIIM_BCM54XX_EXP_SEL_SSD | 0);
 153        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA,
 154                        BMCR_ANRESTART);
 155        /* Enable copper/fiber auto-detect */
 156        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
 157                        MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201));
 158
 159        genphy_config_aneg(phydev);
 160
 161        return 0;
 162}
 163
 164static int bcm_cygnus_startup(struct phy_device *phydev)
 165{
 166        int ret;
 167
 168        /* Read the Status (2x to make sure link is right) */
 169        ret = genphy_update_link(phydev);
 170        if (ret)
 171                return ret;
 172
 173        return genphy_parse_link(phydev);
 174}
 175
 176static void bcm_cygnus_afe(struct phy_device *phydev)
 177{
 178        /* ensures smdspclk is enabled */
 179        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 0x0c30);
 180
 181        /* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */
 182        bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);
 183
 184        /* AFE_HPF_TRIM_OTHERS bit11=1, short cascode for all modes*/
 185        bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);
 186
 187        /* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */
 188        bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);
 189
 190        /* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */
 191        bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);
 192
 193        /* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */
 194        bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);
 195
 196        /* Adjust bias current trim to overcome digital offSet */
 197        phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x02);
 198
 199        /* make rcal=100, since rdb default is 000 */
 200        phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B1);
 201        phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010);
 202
 203        /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */
 204        phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0);
 205        phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010);
 206
 207        /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */
 208        phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0);
 209        phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0000);
 210}
 211
 212static int bcm_cygnus_config(struct phy_device *phydev)
 213{
 214        genphy_config_aneg(phydev);
 215        phy_reset(phydev);
 216        /* AFE settings for PHY stability */
 217        bcm_cygnus_afe(phydev);
 218        /* Forcing aneg after applying the AFE settings */
 219        genphy_restart_aneg(phydev);
 220
 221        return 0;
 222}
 223
 224/*
 225 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
 226 * 0x42 - "Operating Mode Status Register"
 227 */
 228static int bcm5482_is_serdes(struct phy_device *phydev)
 229{
 230        u16 val;
 231        int serdes = 0;
 232
 233        phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
 234                        MIIM_BCM54XX_EXP_SEL_ER | 0x42);
 235        val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
 236
 237        switch (val & 0x1f) {
 238        case 0x0d:      /* RGMII-to-100Base-FX */
 239        case 0x0e:      /* RGMII-to-SGMII */
 240        case 0x0f:      /* RGMII-to-SerDes */
 241        case 0x12:      /* SGMII-to-SerDes */
 242        case 0x13:      /* SGMII-to-100Base-FX */
 243        case 0x16:      /* SerDes-to-Serdes */
 244                serdes = 1;
 245                break;
 246        case 0x6:       /* RGMII-to-Copper */
 247        case 0x14:      /* SGMII-to-Copper */
 248        case 0x17:      /* SerDes-to-Copper */
 249                break;
 250        default:
 251                printf("ERROR, invalid PHY mode (0x%x\n)", val);
 252                break;
 253        }
 254
 255        return serdes;
 256}
 257
 258/*
 259 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
 260 * Mode Status Register"
 261 */
 262static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev)
 263{
 264        u16 val;
 265        int i = 0;
 266
 267        /* Wait 1s for link - Clause 37 autonegotiation happens very fast */
 268        while (1) {
 269                phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
 270                                MIIM_BCM54XX_EXP_SEL_ER | 0x42);
 271                val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
 272
 273                if (val & 0x8000)
 274                        break;
 275
 276                if (i++ > 1000) {
 277                        phydev->link = 0;
 278                        return 1;
 279                }
 280
 281                udelay(1000);   /* 1 ms */
 282        }
 283
 284        phydev->link = 1;
 285        switch ((val >> 13) & 0x3) {
 286        case (0x00):
 287                phydev->speed = 10;
 288                break;
 289        case (0x01):
 290                phydev->speed = 100;
 291                break;
 292        case (0x02):
 293                phydev->speed = 1000;
 294                break;
 295        }
 296
 297        phydev->duplex = (val & 0x1000) == 0x1000;
 298
 299        return 0;
 300}
 301
 302/*
 303 * Figure out if BCM5482 is in serdes or copper mode and determine link
 304 * configuration accordingly
 305 */
 306static int bcm5482_startup(struct phy_device *phydev)
 307{
 308        int ret;
 309
 310        if (bcm5482_is_serdes(phydev)) {
 311                bcm5482_parse_serdes_sr(phydev);
 312                phydev->port = PORT_FIBRE;
 313                return 0;
 314        }
 315
 316        /* Wait for auto-negotiation to complete or fail */
 317        ret = genphy_update_link(phydev);
 318        if (ret)
 319                return ret;
 320
 321        /* Parse BCM54xx copper aux status register */
 322        return bcm54xx_parse_status(phydev);
 323}
 324
 325static struct phy_driver BCM5461S_driver = {
 326        .name = "Broadcom BCM5461S",
 327        .uid = 0x2060c0,
 328        .mask = 0xfffff0,
 329        .features = PHY_GBIT_FEATURES,
 330        .config = &bcm5461_config,
 331        .startup = &bcm54xx_startup,
 332        .shutdown = &genphy_shutdown,
 333};
 334
 335static struct phy_driver BCM5464S_driver = {
 336        .name = "Broadcom BCM5464S",
 337        .uid = 0x2060b0,
 338        .mask = 0xfffff0,
 339        .features = PHY_GBIT_FEATURES,
 340        .config = &bcm5461_config,
 341        .startup = &bcm54xx_startup,
 342        .shutdown = &genphy_shutdown,
 343};
 344
 345static struct phy_driver BCM5482S_driver = {
 346        .name = "Broadcom BCM5482S",
 347        .uid = 0x143bcb0,
 348        .mask = 0xffffff0,
 349        .features = PHY_GBIT_FEATURES,
 350        .config = &bcm5482_config,
 351        .startup = &bcm5482_startup,
 352        .shutdown = &genphy_shutdown,
 353};
 354
 355static struct phy_driver BCM_CYGNUS_driver = {
 356        .name = "Broadcom CYGNUS GPHY",
 357        .uid = 0xae025200,
 358        .mask = 0xfffff0,
 359        .features = PHY_GBIT_FEATURES,
 360        .config = &bcm_cygnus_config,
 361        .startup = &bcm_cygnus_startup,
 362        .shutdown = &genphy_shutdown,
 363};
 364
 365int phy_broadcom_init(void)
 366{
 367        phy_register(&BCM5482S_driver);
 368        phy_register(&BCM5464S_driver);
 369        phy_register(&BCM5461S_driver);
 370        phy_register(&BCM_CYGNUS_driver);
 371
 372        return 0;
 373}
 374