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7
8#include <common.h>
9#include <command.h>
10#include <console.h>
11
12#include <dm.h>
13#include <dm/lists.h>
14
15#include <net.h>
16#include <phy.h>
17#include <errno.h>
18#include <miiphy.h>
19#include <malloc.h>
20#include <asm/ti-common/keystone_nav.h>
21#include <asm/ti-common/keystone_net.h>
22#include <asm/ti-common/keystone_serdes.h>
23#include <asm/arch/psc_defs.h>
24
25#include "cpsw_mdio.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#ifdef KEYSTONE2_EMAC_GIG_ENABLE
30#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
31#else
32#define emac_gigabit_enable(x)
33#endif
34
35#define RX_BUFF_NUMS 24
36#define RX_BUFF_LEN 1520
37#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
38#define SGMII_ANEG_TIMEOUT 4000
39
40static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
41
42enum link_type {
43 LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
44 LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
45 LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
46 LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
47 LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
48 LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
49 LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
50 LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
51 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
52 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
53};
54
55#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
56 ((mac)[2] << 16) | ((mac)[3] << 24))
57#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
58
59#ifdef CONFIG_KSNET_NETCP_V1_0
60
61#define EMAC_EMACSW_BASE_OFS 0x90800
62#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
63
64
65#define CPGMACSL_REG_SA_LO 0x10
66#define CPGMACSL_REG_SA_HI 0x14
67
68#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
69 (x) * 0x30)
70
71#elif defined(CONFIG_KSNET_NETCP_V1_5)
72
73#define EMAC_EMACSW_PORT_BASE_OFS 0x222000
74
75
76#define CPGMACSL_REG_SA_LO 0x308
77#define CPGMACSL_REG_SA_HI 0x30c
78
79#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
80 (x) * 0x1000)
81
82#endif
83
84
85struct ks2_eth_priv {
86 struct udevice *dev;
87 struct phy_device *phydev;
88 struct mii_dev *mdio_bus;
89 int phy_addr;
90 phy_interface_t phy_if;
91 int phy_of_handle;
92 int sgmii_link_type;
93 void *mdio_base;
94 struct rx_buff_desc net_rx_buffs;
95 struct pktdma_cfg *netcp_pktdma;
96 void *hd;
97 int slave_port;
98 enum link_type link_type;
99 bool emac_open;
100 bool has_mdio;
101};
102
103static void __attribute__((unused))
104 keystone2_eth_gigabit_enable(struct udevice *dev)
105{
106 struct ks2_eth_priv *priv = dev_get_priv(dev);
107
108
109
110
111
112 if (priv->has_mdio) {
113 if (priv->phydev->speed != 1000)
114 return;
115 }
116
117 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
118 CPGMACSL_REG_CTL) |
119 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
120 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
121}
122
123#ifdef CONFIG_SOC_K2G
124int keystone_rgmii_config(struct phy_device *phy_dev)
125{
126 unsigned int i, status;
127
128 i = 0;
129 do {
130 if (i > SGMII_ANEG_TIMEOUT) {
131 puts(" TIMEOUT !\n");
132 phy_dev->link = 0;
133 return 0;
134 }
135
136 if (ctrlc()) {
137 puts("user interrupt!\n");
138 phy_dev->link = 0;
139 return -EINTR;
140 }
141
142 if ((i++ % 500) == 0)
143 printf(".");
144
145 udelay(1000);
146 status = readl(RGMII_STATUS_REG);
147 } while (!(status & RGMII_REG_STATUS_LINK));
148
149 puts(" done\n");
150
151 return 0;
152}
153#else
154int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
155{
156 unsigned int i, status, mask;
157 unsigned int mr_adv_ability, control;
158
159 switch (interface) {
160 case SGMII_LINK_MAC_MAC_AUTONEG:
161 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
162 SGMII_REG_MR_ADV_LINK |
163 SGMII_REG_MR_ADV_FULL_DUPLEX |
164 SGMII_REG_MR_ADV_GIG_MODE);
165 control = (SGMII_REG_CONTROL_MASTER |
166 SGMII_REG_CONTROL_AUTONEG);
167
168 break;
169 case SGMII_LINK_MAC_PHY:
170 case SGMII_LINK_MAC_PHY_FORCED:
171 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
172 control = SGMII_REG_CONTROL_AUTONEG;
173
174 break;
175 case SGMII_LINK_MAC_MAC_FORCED:
176 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
177 SGMII_REG_MR_ADV_LINK |
178 SGMII_REG_MR_ADV_FULL_DUPLEX |
179 SGMII_REG_MR_ADV_GIG_MODE);
180 control = SGMII_REG_CONTROL_MASTER;
181
182 break;
183 case SGMII_LINK_MAC_FIBER:
184 mr_adv_ability = 0x20;
185 control = SGMII_REG_CONTROL_AUTONEG;
186
187 break;
188 default:
189 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
190 control = SGMII_REG_CONTROL_AUTONEG;
191 }
192
193 __raw_writel(0, SGMII_CTL_REG(port));
194
195
196
197
198
199 for (i = 0; i < 1000; i++) {
200 udelay(2000);
201 status = __raw_readl(SGMII_STATUS_REG(port));
202 if ((status & SGMII_REG_STATUS_LOCK) != 0)
203 break;
204 }
205
206 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
207 __raw_writel(control, SGMII_CTL_REG(port));
208
209
210 mask = SGMII_REG_STATUS_LINK;
211
212 if (control & SGMII_REG_CONTROL_AUTONEG)
213 mask |= SGMII_REG_STATUS_AUTONEG;
214
215 status = __raw_readl(SGMII_STATUS_REG(port));
216 if ((status & mask) == mask)
217 return 0;
218
219 printf("\n%s Waiting for SGMII auto negotiation to complete",
220 phy_dev->dev->name);
221 while ((status & mask) != mask) {
222
223
224
225 if (i > SGMII_ANEG_TIMEOUT) {
226 puts(" TIMEOUT !\n");
227 phy_dev->link = 0;
228 return 0;
229 }
230
231 if (ctrlc()) {
232 puts("user interrupt!\n");
233 phy_dev->link = 0;
234 return -EINTR;
235 }
236
237 if ((i++ % 500) == 0)
238 printf(".");
239
240 udelay(1000);
241 status = __raw_readl(SGMII_STATUS_REG(port));
242 }
243 puts(" done\n");
244
245 return 0;
246}
247#endif
248
249int mac_sl_reset(u32 port)
250{
251 u32 i, v;
252
253 if (port >= DEVICE_N_GMACSL_PORTS)
254 return GMACSL_RET_INVALID_PORT;
255
256
257 writel(CPGMAC_REG_RESET_VAL_RESET,
258 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
259
260
261 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
262 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
263 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
264 CPGMAC_REG_RESET_VAL_RESET)
265 return GMACSL_RET_OK;
266 }
267
268
269 return GMACSL_RET_WARN_RESET_INCOMPLETE;
270}
271
272int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
273{
274 u32 v, i;
275 int ret = GMACSL_RET_OK;
276
277 if (port >= DEVICE_N_GMACSL_PORTS)
278 return GMACSL_RET_INVALID_PORT;
279
280 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
281 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
282 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
283 }
284
285
286 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
287 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
288 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
289 CPGMAC_REG_RESET_VAL_RESET)
290 break;
291 }
292
293 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
294 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
295
296 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
297 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
298
299#ifndef CONFIG_SOC_K2HK
300
301 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
302#endif
303
304 return ret;
305}
306
307int ethss_config(u32 ctl, u32 max_pkt_size)
308{
309 u32 i;
310
311
312 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
313
314
315 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
316
317
318 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
319 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
320
321
322 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
323 CPSW_REG_VAL_ALE_CTL_BYPASS,
324 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
325
326
327 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
328 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
329 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
330
331 return 0;
332}
333
334int ethss_start(void)
335{
336 int i;
337 struct mac_sl_cfg cfg;
338
339 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
340 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
341
342 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
343 mac_sl_reset(i);
344 mac_sl_config(i, &cfg);
345 }
346
347 return 0;
348}
349
350int ethss_stop(void)
351{
352 int i;
353
354 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
355 mac_sl_reset(i);
356
357 return 0;
358}
359
360struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
361 .clk = SERDES_CLOCK_156P25M,
362 .rate = SERDES_RATE_5G,
363 .rate_mode = SERDES_QUARTER_RATE,
364 .intf = SERDES_PHY_SGMII,
365 .loopback = 0,
366};
367
368#ifndef CONFIG_SOC_K2G
369static void keystone2_net_serdes_setup(void)
370{
371 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
372 &ks2_serdes_sgmii_156p25mhz,
373 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
374
375#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
376 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
377 &ks2_serdes_sgmii_156p25mhz,
378 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
379#endif
380
381
382 udelay(5000);
383}
384#endif
385
386static int ks2_eth_start(struct udevice *dev)
387{
388 struct ks2_eth_priv *priv = dev_get_priv(dev);
389
390#ifdef CONFIG_SOC_K2G
391 keystone_rgmii_config(priv->phydev);
392#else
393 keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
394 priv->sgmii_link_type);
395#endif
396
397 udelay(10000);
398
399
400 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
401
402 qm_init();
403
404 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
405 pr_err("ksnav_init failed\n");
406 goto err_knav_init;
407 }
408
409
410
411
412
413
414 hw_config_streaming_switch();
415
416 if (priv->has_mdio) {
417 phy_startup(priv->phydev);
418 if (priv->phydev->link == 0) {
419 pr_err("phy startup failed\n");
420 goto err_phy_start;
421 }
422 }
423
424 emac_gigabit_enable(dev);
425
426 ethss_start();
427
428 priv->emac_open = true;
429
430 return 0;
431
432err_phy_start:
433 ksnav_close(priv->netcp_pktdma);
434err_knav_init:
435 qm_close();
436
437 return -EFAULT;
438}
439
440static int ks2_eth_send(struct udevice *dev, void *packet, int length)
441{
442 struct ks2_eth_priv *priv = dev_get_priv(dev);
443
444 genphy_update_link(priv->phydev);
445 if (priv->phydev->link == 0)
446 return -1;
447
448 if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
449 length = EMAC_MIN_ETHERNET_PKT_SIZE;
450
451 return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
452 length, (priv->slave_port) << 16);
453}
454
455static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
456{
457 struct ks2_eth_priv *priv = dev_get_priv(dev);
458 int pkt_size;
459 u32 *pkt = NULL;
460
461 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
462 if (priv->hd == NULL)
463 return -EAGAIN;
464
465 *packetp = (uchar *)pkt;
466
467 return pkt_size;
468}
469
470static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
471 int length)
472{
473 struct ks2_eth_priv *priv = dev_get_priv(dev);
474
475 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
476
477 return 0;
478}
479
480static void ks2_eth_stop(struct udevice *dev)
481{
482 struct ks2_eth_priv *priv = dev_get_priv(dev);
483
484 if (!priv->emac_open)
485 return;
486 ethss_stop();
487
488 ksnav_close(priv->netcp_pktdma);
489 qm_close();
490 phy_shutdown(priv->phydev);
491 priv->emac_open = false;
492}
493
494int ks2_eth_read_rom_hwaddr(struct udevice *dev)
495{
496 struct ks2_eth_priv *priv = dev_get_priv(dev);
497 struct eth_pdata *pdata = dev_get_platdata(dev);
498 u32 maca = 0;
499 u32 macb = 0;
500
501
502 if (priv->slave_port == 1) {
503 maca = __raw_readl(MAC_ID_BASE_ADDR);
504 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
505 }
506
507 pdata->enetaddr[0] = (macb >> 8) & 0xff;
508 pdata->enetaddr[1] = (macb >> 0) & 0xff;
509 pdata->enetaddr[2] = (maca >> 24) & 0xff;
510 pdata->enetaddr[3] = (maca >> 16) & 0xff;
511 pdata->enetaddr[4] = (maca >> 8) & 0xff;
512 pdata->enetaddr[5] = (maca >> 0) & 0xff;
513
514 return 0;
515}
516
517int ks2_eth_write_hwaddr(struct udevice *dev)
518{
519 struct ks2_eth_priv *priv = dev_get_priv(dev);
520 struct eth_pdata *pdata = dev_get_platdata(dev);
521
522 writel(mac_hi(pdata->enetaddr),
523 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
524 CPGMACSL_REG_SA_HI);
525 writel(mac_lo(pdata->enetaddr),
526 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
527 CPGMACSL_REG_SA_LO);
528
529 return 0;
530}
531
532static int ks2_eth_probe(struct udevice *dev)
533{
534 struct ks2_eth_priv *priv = dev_get_priv(dev);
535 struct mii_dev *mdio_bus;
536
537 priv->dev = dev;
538 priv->emac_open = false;
539
540
541 if (cpu_is_k2g())
542 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
543
544
545#ifndef CONFIG_SOC_K2G
546 if (psc_enable_module(KS2_LPSC_PA))
547 return -EACCES;
548#endif
549 if (psc_enable_module(KS2_LPSC_CPGMAC))
550 return -EACCES;
551 if (psc_enable_module(KS2_LPSC_CRYPTO))
552 return -EACCES;
553
554 if (cpu_is_k2e() || cpu_is_k2l())
555 pll_pa_clk_sel();
556
557 priv->net_rx_buffs.buff_ptr = rx_buffs;
558 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
559 priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
560
561 if (priv->slave_port == 1) {
562#ifndef CONFIG_SOC_K2G
563 keystone2_net_serdes_setup();
564#endif
565
566
567
568
569 mdio_bus = cpsw_mdio_init("ethernet-mdio",
570 (u32)priv->mdio_base,
571 EMAC_MDIO_CLOCK_FREQ,
572 EMAC_MDIO_BUS_FREQ);
573 if (!mdio_bus) {
574 pr_err("MDIO alloc failed\n");
575 return -ENOMEM;
576 }
577 priv->mdio_bus = mdio_bus;
578 } else {
579
580 struct ks2_eth_priv *parent_priv;
581
582 parent_priv = dev_get_priv(dev->parent);
583 priv->mdio_bus = parent_priv->mdio_bus;
584 priv->mdio_base = parent_priv->mdio_base;
585 }
586
587 priv->netcp_pktdma = &netcp_pktdma;
588
589 if (priv->has_mdio) {
590 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
591 dev, priv->phy_if);
592#ifdef CONFIG_DM_ETH
593 if (priv->phy_of_handle)
594 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
595#endif
596 phy_config(priv->phydev);
597 }
598
599 return 0;
600}
601
602int ks2_eth_remove(struct udevice *dev)
603{
604 struct ks2_eth_priv *priv = dev_get_priv(dev);
605
606 cpsw_mdio_free(priv->mdio_bus);
607
608 return 0;
609}
610
611static const struct eth_ops ks2_eth_ops = {
612 .start = ks2_eth_start,
613 .send = ks2_eth_send,
614 .recv = ks2_eth_recv,
615 .free_pkt = ks2_eth_free_pkt,
616 .stop = ks2_eth_stop,
617 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
618 .write_hwaddr = ks2_eth_write_hwaddr,
619};
620
621static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
622{
623 const void *fdt = gd->fdt_blob;
624 struct udevice *sl_dev;
625 int interfaces;
626 int sec_slave;
627 int slave;
628 int ret;
629 char *slave_name;
630
631 interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
632 fdt_for_each_subnode(slave, fdt, interfaces) {
633 int slave_no;
634
635 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
636 if (slave_no == -ENOENT)
637 continue;
638
639 if (slave_no == 0) {
640
641 *gbe_0 = slave;
642 } else {
643
644 slave_name = malloc(20);
645 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
646 ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
647 slave_name, offset_to_ofnode(slave),
648 &sl_dev);
649 if (ret) {
650 pr_err("ks2_net - not able to bind slave interfaces\n");
651 return ret;
652 }
653 }
654 }
655
656 sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
657 fdt_for_each_subnode(slave, fdt, sec_slave) {
658 int slave_no;
659
660 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
661 if (slave_no == -ENOENT)
662 continue;
663
664
665 slave_name = malloc(20);
666 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
667 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
668 offset_to_ofnode(slave), &sl_dev);
669 if (ret) {
670 pr_err("ks2_net - not able to bind slave interfaces\n");
671 return ret;
672 }
673 }
674
675 return 0;
676}
677
678static int ks2_eth_parse_slave_interface(int netcp, int slave,
679 struct ks2_eth_priv *priv,
680 struct eth_pdata *pdata)
681{
682 const void *fdt = gd->fdt_blob;
683 int mdio;
684 int phy;
685 int dma_count;
686 u32 dma_channel[8];
687 const char *phy_mode;
688
689 priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
690 priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
691
692
693 priv->slave_port += 1;
694
695 dma_count = fdtdec_get_int_array_count(fdt, netcp,
696 "ti,navigator-dmas",
697 dma_channel, 8);
698
699 if (dma_count > (2 * priv->slave_port)) {
700 int dma_idx;
701
702 dma_idx = priv->slave_port * 2 - 1;
703 priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
704 }
705
706 priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
707
708 phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
709
710 if (phy >= 0) {
711 priv->phy_of_handle = phy;
712 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
713
714 mdio = fdt_parent_offset(fdt, phy);
715 if (mdio < 0) {
716 pr_err("mdio dt not found\n");
717 return -ENODEV;
718 }
719 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
720 }
721
722 if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
723 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
724 pdata->phy_interface = priv->phy_if;
725 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
726 priv->has_mdio = true;
727 } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
728 phy_mode = fdt_getprop(fdt, slave, "phy-mode", NULL);
729 if (phy_mode) {
730 priv->phy_if = phy_get_interface_by_name(phy_mode);
731 if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
732 priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
733 priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
734 priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
735 pr_err("invalid phy-mode\n");
736 return -EINVAL;
737 }
738 } else {
739 priv->phy_if = PHY_INTERFACE_MODE_RGMII;
740 }
741 pdata->phy_interface = priv->phy_if;
742 priv->has_mdio = true;
743 }
744
745 return 0;
746}
747
748static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
749{
750 struct ks2_eth_priv *priv = dev_get_priv(dev);
751 struct eth_pdata *pdata = dev_get_platdata(dev);
752 const void *fdt = gd->fdt_blob;
753 int slave = dev_of_offset(dev);
754 int interfaces;
755 int gbe;
756 int netcp_devices;
757 int netcp;
758
759 interfaces = fdt_parent_offset(fdt, slave);
760 gbe = fdt_parent_offset(fdt, interfaces);
761 netcp_devices = fdt_parent_offset(fdt, gbe);
762 netcp = fdt_parent_offset(fdt, netcp_devices);
763
764 ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
765
766 pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
767
768 return 0;
769}
770
771static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
772{
773 struct ks2_eth_priv *priv = dev_get_priv(dev);
774 struct eth_pdata *pdata = dev_get_platdata(dev);
775 const void *fdt = gd->fdt_blob;
776 int gbe_0 = -ENODEV;
777 int netcp_devices;
778 int gbe;
779
780 netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
781 "netcp-devices");
782 gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
783
784 ks2_eth_bind_slaves(dev, gbe, &gbe_0);
785
786 ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
787
788 pdata->iobase = devfdt_get_addr(dev);
789
790 return 0;
791}
792
793static const struct udevice_id ks2_eth_ids[] = {
794 { .compatible = "ti,netcp-1.0" },
795 { }
796};
797
798U_BOOT_DRIVER(eth_ks2_slave) = {
799 .name = "eth_ks2_sl",
800 .id = UCLASS_ETH,
801 .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
802 .probe = ks2_eth_probe,
803 .remove = ks2_eth_remove,
804 .ops = &ks2_eth_ops,
805 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
806 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
807 .flags = DM_FLAG_ALLOC_PRIV_DMA,
808};
809
810U_BOOT_DRIVER(eth_ks2) = {
811 .name = "eth_ks2",
812 .id = UCLASS_ETH,
813 .of_match = ks2_eth_ids,
814 .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
815 .probe = ks2_eth_probe,
816 .remove = ks2_eth_remove,
817 .ops = &ks2_eth_ops,
818 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
819 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
820 .flags = DM_FLAG_ALLOC_PRIV_DMA,
821};
822
