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7#include <common.h>
8#include <usb.h>
9#include <errno.h>
10#include <linux/compiler.h>
11#include <usb/ehci-ci.h>
12#include <asm/io.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/clock.h>
15#include <dm.h>
16#include <power/regulator.h>
17
18#include "ehci.h"
19
20#define MX5_USBOTHER_REGS_OFFSET 0x800
21
22
23#define MXC_OTG_OFFSET 0
24#define MXC_H1_OFFSET 0x200
25#define MXC_H2_OFFSET 0x400
26#define MXC_H3_OFFSET 0x600
27
28#define MXC_USBCTRL_OFFSET 0
29#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
30#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
31#define MXC_USB_CTRL_1_OFFSET 0x10
32#define MXC_USBH2CTRL_OFFSET 0x14
33#define MXC_USBH3CTRL_OFFSET 0x18
34
35
36
37#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
38
39#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
40
41#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
42
43#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
44
45#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
46
47#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
48
49#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
50
51
52
53#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
54
55#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
56
57#define MXC_H1_OC_POL_BIT (1 << 6)
58
59#define MXC_H1_OC_DIS_BIT (1 << 5)
60
61#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
62
63
64#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
65#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
66#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
67#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
68#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
69#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
70
71
72#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
73#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
74#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
75#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
76#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
77
78
79#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
80
81int mxc_set_usbcontrol(int port, unsigned int flags)
82{
83 unsigned int v;
84 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
85 void __iomem *usbother_base;
86 int ret = 0;
87
88 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
89
90 switch (port) {
91 case 0:
92 if (flags & MXC_EHCI_INTERNAL_PHY) {
93 v = __raw_readl(usbother_base +
94 MXC_USB_PHY_CTR_FUNC_OFFSET);
95 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
96 v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
97 else
98 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
99 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
100
101 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
102 else
103
104 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
105#ifdef CONFIG_MX51
106 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
107 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
108 else
109 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
110#endif
111 __raw_writel(v, usbother_base +
112 MXC_USB_PHY_CTR_FUNC_OFFSET);
113
114 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
115#ifdef CONFIG_MX51
116 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
117 v &= ~MXC_OTG_UCTRL_OPM_BIT;
118 else
119 v |= MXC_OTG_UCTRL_OPM_BIT;
120#endif
121#ifdef CONFIG_MX53
122 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
123 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
124 else
125 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
126#endif
127 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
128 }
129 break;
130 case 1:
131#ifdef CONFIG_MX51
132
133
134 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
135 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
136 MXC_USB_CTRL_1_OFFSET);
137#endif
138
139 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
140#ifdef CONFIG_MX51
141 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
142 v &= ~MXC_H1_UCTRL_H1PM_BIT;
143 else
144 v |= MXC_H1_UCTRL_H1PM_BIT;
145#endif
146#ifdef CONFIG_MX53
147 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
148 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
149 else
150 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
151#endif
152 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
153
154 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
155 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
156 v |= MXC_H1_OC_POL_BIT;
157 else
158 v &= ~MXC_H1_OC_POL_BIT;
159 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
160 v &= ~MXC_H1_OC_DIS_BIT;
161 else
162 v |= MXC_H1_OC_DIS_BIT;
163 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
164
165 break;
166 case 2:
167 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
168#ifdef CONFIG_MX51
169 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
170 v &= ~MXC_H2_UCTRL_H2PM_BIT;
171 else
172 v |= MXC_H2_UCTRL_H2PM_BIT;
173#endif
174#ifdef CONFIG_MX53
175 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
176 v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
177 else
178 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
179 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
180 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT;
181 else
182 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT;
183 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
184 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
185 else
186 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
187#endif
188 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
189 break;
190#ifdef CONFIG_MX53
191 case 3:
192 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
193 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
194 v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
195 else
196 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
197 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
198 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT;
199 else
200 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT;
201 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
202 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
203 else
204 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
205 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
206 break;
207#endif
208 }
209
210 return ret;
211}
212
213int __weak board_ehci_hcd_init(int port)
214{
215 return 0;
216}
217
218void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
219{
220}
221
222__weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
223 uint32_t *reg)
224{
225 mdelay(50);
226}
227
228#if !CONFIG_IS_ENABLED(DM_USB)
229static const struct ehci_ops mx5_ehci_ops = {
230 .powerup_fixup = mx5_ehci_powerup_fixup,
231};
232
233int ehci_hcd_init(int index, enum usb_init_type init,
234 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
235{
236 struct usb_ehci *ehci;
237
238
239 ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
240 set_usboh3_clk();
241 enable_usboh3_clk(true);
242 set_usb_phy_clk();
243 enable_usb_phy1_clk(true);
244 enable_usb_phy2_clk(true);
245 mdelay(1);
246
247
248 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
249
250 ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
251 (0x200 * CONFIG_MXC_USB_PORT));
252 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
253 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
254 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
255 setbits_le32(&ehci->usbmode, CM_HOST);
256
257 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
258 setbits_le32(&ehci->portsc, USB_EN);
259
260 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
261 mdelay(10);
262
263
264 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
265
266 return 0;
267}
268
269int ehci_hcd_stop(int index)
270{
271 return 0;
272}
273#else
274struct ehci_mx5_priv_data {
275 struct ehci_ctrl ctrl;
276 struct usb_ehci *ehci;
277 struct udevice *vbus_supply;
278 enum usb_init_type init_type;
279 int portnr;
280};
281
282static const struct ehci_ops mx5_ehci_ops = {
283 .powerup_fixup = mx5_ehci_powerup_fixup,
284};
285
286static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
287{
288 struct usb_platdata *plat = dev_get_platdata(dev);
289 const char *mode;
290
291 mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
292 if (mode) {
293 if (strcmp(mode, "peripheral") == 0)
294 plat->init_type = USB_INIT_DEVICE;
295 else if (strcmp(mode, "host") == 0)
296 plat->init_type = USB_INIT_HOST;
297 else
298 return -EINVAL;
299 }
300
301 return 0;
302}
303
304static int ehci_usb_probe(struct udevice *dev)
305{
306 struct usb_platdata *plat = dev_get_platdata(dev);
307 struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
308 struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
309 enum usb_init_type type = plat->init_type;
310 struct ehci_hccr *hccr;
311 struct ehci_hcor *hcor;
312 int ret;
313
314 set_usboh3_clk();
315 enable_usboh3_clk(true);
316 set_usb_phy_clk();
317 enable_usb_phy1_clk(true);
318 enable_usb_phy2_clk(true);
319 mdelay(1);
320
321 priv->ehci = ehci;
322 priv->portnr = dev->seq;
323 priv->init_type = type;
324
325 ret = device_get_supply_regulator(dev, "vbus-supply",
326 &priv->vbus_supply);
327 if (ret)
328 debug("%s: No vbus supply\n", dev->name);
329
330 if (!ret && priv->vbus_supply) {
331 ret = regulator_set_enable(priv->vbus_supply,
332 (type == USB_INIT_DEVICE) ?
333 false : true);
334 if (ret) {
335 puts("Error enabling VBUS supply\n");
336 return ret;
337 }
338 }
339
340 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
341 hcor = (struct ehci_hcor *)((uint32_t)hccr +
342 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
343 setbits_le32(&ehci->usbmode, CM_HOST);
344
345 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
346 setbits_le32(&ehci->portsc, USB_EN);
347
348 mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
349 mdelay(10);
350
351 return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
352 priv->init_type);
353}
354
355static const struct udevice_id mx5_usb_ids[] = {
356 { .compatible = "fsl,imx53-usb" },
357 { }
358};
359
360U_BOOT_DRIVER(usb_mx5) = {
361 .name = "ehci_mx5",
362 .id = UCLASS_USB,
363 .of_match = mx5_usb_ids,
364 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
365 .probe = ehci_usb_probe,
366 .remove = ehci_deregister,
367 .ops = &ehci_usb_ops,
368 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
369 .priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data),
370 .flags = DM_FLAG_ALLOC_PRIV_DMA,
371};
372#endif
373
