1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Toradex Colibri PXA270 configuration file 4 * 5 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 6 * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com> 7 */ 8 9#ifndef __CONFIG_H 10#define __CONFIG_H 11 12/* 13 * High Level Board Configuration Options 14 */ 15#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 16/* Avoid overwriting factory configuration block */ 17#define CONFIG_BOARD_SIZE_LIMIT 0x40000 18 19/* 20 * Environment settings 21 */ 22#define CONFIG_ENV_OVERWRITE 23#define CONFIG_SYS_MALLOC_LEN (128 * 1024) 24#define CONFIG_ARCH_CPU_INIT 25#define CONFIG_BOOTCOMMAND \ 26 "if fatload mmc 0 0xa0000000 uImage; then " \ 27 "bootm 0xa0000000; " \ 28 "fi; " \ 29 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ 30 "bootm 0xa0000000; " \ 31 "fi; " \ 32 "bootm 0xc0000;" 33#define CONFIG_TIMESTAMP 34#define CONFIG_CMDLINE_TAG 35#define CONFIG_SETUP_MEMORY_TAGS 36 37/* 38 * Serial Console Configuration 39 */ 40 41/* 42 * Bootloader Components Configuration 43 */ 44 45/* I2C support */ 46#ifdef CONFIG_SYS_I2C 47#define CONFIG_SYS_I2C_PXA 48#define CONFIG_PXA_STD_I2C 49#define CONFIG_PXA_PWR_I2C 50#define CONFIG_SYS_I2C_SPEED 100000 51#endif 52 53/* LCD support */ 54#ifdef CONFIG_LCD 55#define CONFIG_PXA_LCD 56#define CONFIG_PXA_VGA 57#define CONFIG_LCD_LOGO 58#endif 59 60/* 61 * Networking Configuration 62 */ 63#ifdef CONFIG_CMD_NET 64 65#define CONFIG_DRIVER_DM9000 1 66#define CONFIG_DM9000_BASE 0x08000000 67#define DM9000_IO (CONFIG_DM9000_BASE) 68#define DM9000_DATA (CONFIG_DM9000_BASE + 4) 69#define CONFIG_NET_RETRY_COUNT 10 70 71#define CONFIG_BOOTP_BOOTFILESIZE 72#endif 73 74#define CONFIG_SYS_DEVICE_NULLDEV 1 75 76/* 77 * Clock Configuration 78 */ 79#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ 80 81/* 82 * DRAM Map 83 */ 84#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 85#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 86 87#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 88#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ 89 90#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 91#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 92 93#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 94#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 95#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 96 97/* 98 * NOR FLASH 99 */ 100#ifdef CONFIG_CMD_FLASH 101#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 102#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 103#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 104 105#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 106 107#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) 108#define CONFIG_SYS_MAX_FLASH_BANKS 1 109 110#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) 111#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) 112#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) 113#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) 114#endif 115 116#define CONFIG_SYS_MONITOR_BASE 0x0 117#define CONFIG_SYS_MONITOR_LEN 0x40000 118 119/* Skip factory configuration block */ 120#define CONFIG_ENV_ADDR \ 121 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) 122#define CONFIG_ENV_SIZE 0x40000 123#define CONFIG_ENV_SECT_SIZE 0x40000 124 125/* 126 * GPIO settings 127 */ 128#define CONFIG_SYS_GPSR0_VAL 0x00000000 129#define CONFIG_SYS_GPSR1_VAL 0x00020000 130#define CONFIG_SYS_GPSR2_VAL 0x0002c000 131#define CONFIG_SYS_GPSR3_VAL 0x00000000 132 133#define CONFIG_SYS_GPCR0_VAL 0x00000000 134#define CONFIG_SYS_GPCR1_VAL 0x00000000 135#define CONFIG_SYS_GPCR2_VAL 0x00000000 136#define CONFIG_SYS_GPCR3_VAL 0x00000000 137 138#define CONFIG_SYS_GPDR0_VAL 0xc8008000 139#define CONFIG_SYS_GPDR1_VAL 0xfc02a981 140#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff 141#define CONFIG_SYS_GPDR3_VAL 0x0061e804 142 143#define CONFIG_SYS_GAFR0_L_VAL 0x80100000 144#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 145#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a 146#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 147#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa 148#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 149#define CONFIG_SYS_GAFR3_L_VAL 0x54000310 150#define CONFIG_SYS_GAFR3_U_VAL 0x00005401 151 152#define CONFIG_SYS_PSSR_VAL 0x30 153 154/* 155 * Clock settings 156 */ 157#define CONFIG_SYS_CKEN 0x00500240 158#define CONFIG_SYS_CCCR 0x02000290 159 160/* 161 * Memory settings 162 */ 163#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 164#define CONFIG_SYS_MSC1_VAL 0x9ee1f994 165#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 166#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 167#define CONFIG_SYS_MDREFR_VAL 0x2003a031 168#define CONFIG_SYS_MDMRS_VAL 0x00220022 169#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 170#define CONFIG_SYS_SXCNFG_VAL 0x40044004 171 172/* 173 * PCMCIA and CF Interfaces 174 */ 175#define CONFIG_SYS_MECR_VAL 0x00000000 176#define CONFIG_SYS_MCMEM0_VAL 0x00028307 177#define CONFIG_SYS_MCMEM1_VAL 0x00014307 178#define CONFIG_SYS_MCATT0_VAL 0x00038787 179#define CONFIG_SYS_MCATT1_VAL 0x0001c787 180#define CONFIG_SYS_MCIO0_VAL 0x0002830f 181#define CONFIG_SYS_MCIO1_VAL 0x0001430f 182 183#include "pxa-common.h" 184 185#endif /* __CONFIG_H */ 186