LXR uboot/include/configs/xpedite550x.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2010 Extreme Engineering Solutions, Inc.
   4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
   5 */
   6
   7/*
   8 * xpedite550x board configuration file
   9 */
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13/*
  14 * High Level Configuration Options
  15 */
  16#define CONFIG_SYS_BOARD_NAME   "XPedite5500"
  17#define CONFIG_SYS_FORM_PMC_XMC 1
  18#define CONFIG_PRPMC_PCI_ALIAS  "pci0"  /* Processor PMC interface on pci0 */
  19
  20#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  21#define CONFIG_PCIE1            1       /* PCIE controller 1 (PEX8112 or XMC) */
  22#define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  23#define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  24#define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  25
  26/*
  27 * Multicore config
  28 */
  29#define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  30#define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  31
  32/*
  33 * DDR config
  34 */
  35#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  36#define CONFIG_DDR_SPD
  37#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  38#define SPD_EEPROM_ADDRESS                      0x54
  39#define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  40#define CONFIG_DIMM_SLOTS_PER_CTLR      1
  41#define CONFIG_CHIP_SELECTS_PER_CTRL 2
  42#define CONFIG_DDR_ECC
  43#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  44#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  45#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  46#define CONFIG_VERY_BIG_RAM
  47
  48#ifndef __ASSEMBLY__
  49extern unsigned long get_board_sys_clk(unsigned long dummy);
  50extern unsigned long get_board_ddr_clk(unsigned long dummy);
  51#endif
  52
  53#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  54#define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  55
  56/*
  57 * These can be toggled for performance analysis, otherwise use default.
  58 */
  59#define CONFIG_L2_CACHE                 /* toggle L2 cache */
  60#define CONFIG_BTB                      /* toggle branch predition */
  61#define CONFIG_ENABLE_36BIT_PHYS        1
  62
  63#define CONFIG_SYS_CCSRBAR              0xef000000
  64#define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  65
  66/*
  67 * Diagnostics
  68 */
  69#define CONFIG_SYS_MEMTEST_START        0x10000000
  70#define CONFIG_SYS_MEMTEST_END          0x20000000
  71#define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
  72                                         CONFIG_SYS_POST_I2C)
  73#define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_EEPROM_ADDR,    \
  74                                         CONFIG_SYS_I2C_LM75_ADDR,      \
  75                                         CONFIG_SYS_I2C_LM90_ADDR,      \
  76                                         CONFIG_SYS_I2C_PCA953X_ADDR0,  \
  77                                         CONFIG_SYS_I2C_PCA953X_ADDR2,  \
  78                                         CONFIG_SYS_I2C_PCA953X_ADDR3,  \
  79                                         CONFIG_SYS_I2C_RTC_ADDR}
  80
  81/*
  82 * Memory map
  83 * 0x0000_0000 0x7fff_ffff      DDR                     2G Cacheable
  84 * 0x8000_0000 0xbfff_ffff      PCIe1 Mem               1G non-cacheable
  85 * 0xe000_0000 0xe7ff_ffff      SRAM/SSRAM/L1 Cache     128M non-cacheable
  86 * 0xe800_0000 0xe87f_ffff      PCIe1 IO                8M non-cacheable
  87 * 0xee00_0000 0xee00_ffff      Boot page translation   4K non-cacheable
  88 * 0xef00_0000 0xef0f_ffff      CCSR/IMMR               1M non-cacheable
  89 * 0xef80_0000 0xef8f_ffff      NAND Flash              1M non-cacheable
  90 * 0xf000_0000 0xf7ff_ffff      NOR Flash 2             128M non-cacheable
  91 * 0xf800_0000 0xffff_ffff      NOR Flash 1             128M non-cacheable
  92 */
  93
  94#define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
  95
  96/*
  97 * NAND flash configuration
  98 */
  99#define CONFIG_SYS_NAND_BASE            0xef800000
 100#define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
 101#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 102                                         CONFIG_SYS_NAND_BASE2}
 103#define CONFIG_SYS_MAX_NAND_DEVICE      2
 104#define CONFIG_NAND_FSL_ELBC
 105
 106/*
 107 * NOR flash configuration
 108 */
 109#define CONFIG_SYS_FLASH_BASE           0xf8000000
 110#define CONFIG_SYS_FLASH_BASE2          0xf0000000
 111#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 112#define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 113#define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 114#define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 115#define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 116#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 117                                                  {0xf7f40000, 0xc0000} }
 118#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 119
 120/*
 121 * Chip select configuration
 122 */
 123/* NOR Flash 0 on CS0 */
 124#define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 125                                 BR_PS_16               | \
 126                                 BR_V)
 127#define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 128                                 OR_GPCM_CSNT           | \
 129                                 OR_GPCM_XACS           | \
 130                                 OR_GPCM_ACS_DIV2       | \
 131                                 OR_GPCM_SCY_8          | \
 132                                 OR_GPCM_TRLX           | \
 133                                 OR_GPCM_EHTR           | \
 134                                 OR_GPCM_EAD)
 135
 136/* NOR Flash 1 on CS1 */
 137#define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 138                                 BR_PS_16               | \
 139                                 BR_V)
 140#define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 141
 142/* NAND flash on CS2 */
 143#define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 144                                 (2<<BR_DECC_SHIFT)     | \
 145                                 BR_PS_8                | \
 146                                 BR_MS_FCM              | \
 147                                 BR_V)
 148
 149/* NAND flash on CS2 */
 150#define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 151                                 OR_FCM_PGS     | \
 152                                 OR_FCM_CSCT    | \
 153                                 OR_FCM_CST     | \
 154                                 OR_FCM_CHT     | \
 155                                 OR_FCM_SCY_1   | \
 156                                 OR_FCM_TRLX    | \
 157                                 OR_FCM_EHTR)
 158
 159/* NAND flash on CS3 */
 160#define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 161                                 (2<<BR_DECC_SHIFT)     | \
 162                                 BR_PS_8                | \
 163                                 BR_MS_FCM              | \
 164                                 BR_V)
 165#define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 166
 167/*
 168 * Use L1 as initial stack
 169 */
 170#define CONFIG_SYS_INIT_RAM_LOCK        1
 171#define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 172#define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 173
 174#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 175#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 176
 177#define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 178#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 179
 180/*
 181 * Serial Port
 182 */
 183#define CONFIG_SYS_NS16550_SERIAL
 184#define CONFIG_SYS_NS16550_REG_SIZE     1
 185#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 186#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 187#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 188#define CONFIG_SYS_BAUDRATE_TABLE       \
 189        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 190#define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 191#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 192
 193
 194/*
 195 * I2C
 196 */
 197#define CONFIG_SYS_I2C
 198#define CONFIG_SYS_I2C_FSL
 199#define CONFIG_SYS_FSL_I2C_SPEED        400000
 200#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 201#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 202#define CONFIG_SYS_FSL_I2C2_SPEED       400000
 203#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 204#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 205
 206/* I2C DS7505 temperature sensor */
 207#define CONFIG_SYS_I2C_LM75_ADDR        0x48
 208
 209/* I2C ADT7461 temperature sensor */
 210#define CONFIG_SYS_I2C_LM90_ADDR        0x4C
 211
 212/* I2C EEPROM - AT24C128B */
 213#define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 214#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 215#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 216#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 217
 218/* I2C RTC */
 219#define CONFIG_RTC_M41T11               1
 220#define CONFIG_SYS_I2C_RTC_ADDR         0x68
 221#define CONFIG_SYS_M41T11_BASE_YEAR     2000
 222
 223/* GPIO */
 224#define CONFIG_PCA953X
 225#define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 226#define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 227#define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 228#define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 229#define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 230
 231/*
 232 * GPIO pin definitions, PU = pulled high, PD = pulled low
 233 */
 234/* PCA9557 @ 0x18*/
 235#define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 236#define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
 237#define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 238#define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
 239#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 240#define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Write protection (0: disabled, 1: enabled) */
 241
 242/* PCA9557 @ 0x1e*/
 243#define CONFIG_SYS_PCA953X_XMC_GA0              0x01 /* PU; */
 244#define CONFIG_SYS_PCA953X_XMC_GA1              0x02 /* PU; */
 245#define CONFIG_SYS_PCA953X_XMC_GA2              0x04 /* PU; */
 246#define CONFIG_SYS_PCA953X_XMC_WAKE             0x10 /* PU; */
 247#define CONFIG_SYS_PCA953X_XMC_BIST             0x20 /* Enable XMC BIST */
 248#define CONFIG_SYS_PCA953X_PMC_EREADY           0x40 /* PU; PMC PCI eready */
 249#define CONFIG_SYS_PCA953X_PMC_MONARCH          0x80 /* PMC monarch mode enable */
 250
 251/* PCA9557 @ 0x1f */
 252#define CONFIG_SYS_PCA953X_MC_GPIO0             0x01 /* PU; */
 253#define CONFIG_SYS_PCA953X_MC_GPIO1             0x02 /* PU; */
 254#define CONFIG_SYS_PCA953X_MC_GPIO2             0x04 /* PU; */
 255#define CONFIG_SYS_PCA953X_MC_GPIO3             0x08 /* PU; */
 256#define CONFIG_SYS_PCA953X_MC_GPIO4             0x10 /* PU; */
 257#define CONFIG_SYS_PCA953X_MC_GPIO5             0x20 /* PU; */
 258#define CONFIG_SYS_PCA953X_MC_GPIO6             0x40 /* PU; */
 259#define CONFIG_SYS_PCA953X_MC_GPIO7             0x80 /* PU; */
 260
 261/*
 262 * General PCI
 263 * Memory space is mapped 1-1, but I/O space must start from 0.
 264 */
 265
 266/* controller 1 - PEX8112 or XMC, depending on build option */
 267#define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 268#define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 269#define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 270#define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 271#define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 272#define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 273
 274/*
 275 * Networking options
 276 */
 277#define CONFIG_TSEC_TBI
 278#define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 279#define CONFIG_ETHPRIME         "eTSEC2"
 280
 281/*
 282 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 283 * 1000mbps SGMII link
 284 */
 285#define CONFIG_TSEC_TBICR_SETTINGS ( \
 286                TBICR_PHY_RESET \
 287                | TBICR_FULL_DUPLEX \
 288                | TBICR_SPEED1_SET \
 289                )
 290
 291#define CONFIG_TSEC1            1
 292#define CONFIG_TSEC1_NAME       "eTSEC1"
 293#define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 294#define TSEC1_PHY_ADDR          1
 295#define TSEC1_PHYIDX            0
 296#define CONFIG_HAS_ETH0
 297
 298#define CONFIG_TSEC2            1
 299#define CONFIG_TSEC2_NAME       "eTSEC2"
 300#define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 301#define TSEC2_PHY_ADDR          2
 302#define TSEC2_PHYIDX            0
 303#define CONFIG_HAS_ETH1
 304
 305#define CONFIG_TSEC3            1
 306#define CONFIG_TSEC3_NAME       "eTSEC3"
 307#define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 308#define TSEC3_PHY_ADDR          3
 309#define TSEC3_PHYIDX            0
 310#define CONFIG_HAS_ETH2
 311
 312/*
 313 * USB
 314 */
 315#define CONFIG_USB_EHCI_FSL
 316#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 317
 318/*
 319 * Miscellaneous configurable options
 320 */
 321#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 322#define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 323#define CONFIG_PREBOOT                          /* enable preboot variable */
 324#define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 325
 326/*
 327 * For booting Linux, the board info and command line data
 328 * have to be in the first 16 MB of memory, since this is
 329 * the maximum mapped by the Linux kernel during initialization.
 330 */
 331#define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 332#define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 333
 334/*
 335 * Environment Configuration
 336 */
 337#define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 338#define CONFIG_ENV_SIZE         0x8000
 339#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 340
 341/*
 342 * Flash memory map:
 343 * fff80000 - ffffffff     Pri U-Boot (512 KB)
 344 * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 345 * fff00000 - fff3ffff     Pri FDT (256KB)
 346 * fef00000 - ffefffff     Pri OS image (16MB)
 347 * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 348 *
 349 * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 350 * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 351 * f7f00000 - f7f3ffff     Sec FDT (256KB)
 352 * f6f00000 - f7efffff     Sec OS image (16MB)
 353 * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 354 */
 355#define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 356#define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 357#define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 358#define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 359#define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 360#define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 361
 362#define CONFIG_PROG_UBOOT1                                              \
 363        "$download_cmd $loadaddr $ubootfile; "                          \
 364        "if test $? -eq 0; then "                                       \
 365                "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 366                "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 367                "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 368                "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 369                "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 370                "if test $? -ne 0; then "                               \
 371                        "echo PROGRAM FAILED; "                         \
 372                "else; "                                                \
 373                        "echo PROGRAM SUCCEEDED; "                      \
 374                "fi; "                                                  \
 375        "else; "                                                        \
 376                "echo DOWNLOAD FAILED; "                                \
 377        "fi;"
 378
 379#define CONFIG_PROG_UBOOT2                                              \
 380        "$download_cmd $loadaddr $ubootfile; "                          \
 381        "if test $? -eq 0; then "                                       \
 382                "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 383                "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 384                "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 385                "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 386                "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 387                "if test $? -ne 0; then "                               \
 388                        "echo PROGRAM FAILED; "                         \
 389                "else; "                                                \
 390                        "echo PROGRAM SUCCEEDED; "                      \
 391                "fi; "                                                  \
 392        "else; "                                                        \
 393                "echo DOWNLOAD FAILED; "                                \
 394        "fi;"
 395
 396#define CONFIG_BOOT_OS_NET                                              \
 397        "$download_cmd $osaddr $osfile; "                               \
 398        "if test $? -eq 0; then "                                       \
 399                "if test -n $fdtaddr; then "                            \
 400                        "$download_cmd $fdtaddr $fdtfile; "             \
 401                        "if test $? -eq 0; then "                       \
 402                                "bootm $osaddr - $fdtaddr; "            \
 403                        "else; "                                        \
 404                                "echo FDT DOWNLOAD FAILED; "            \
 405                        "fi; "                                          \
 406                "else; "                                                \
 407                        "bootm $osaddr; "                               \
 408                "fi; "                                                  \
 409        "else; "                                                        \
 410                "echo OS DOWNLOAD FAILED; "                             \
 411        "fi;"
 412
 413#define CONFIG_PROG_OS1                                                 \
 414        "$download_cmd $osaddr $osfile; "                               \
 415        "if test $? -eq 0; then "                                       \
 416                "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 417                "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 418                "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 419                "if test $? -ne 0; then "                               \
 420                        "echo OS PROGRAM FAILED; "                      \
 421                "else; "                                                \
 422                        "echo OS PROGRAM SUCCEEDED; "                   \
 423                "fi; "                                                  \
 424        "else; "                                                        \
 425                "echo OS DOWNLOAD FAILED; "                             \
 426        "fi;"
 427
 428#define CONFIG_PROG_OS2                                                 \
 429        "$download_cmd $osaddr $osfile; "                               \
 430        "if test $? -eq 0; then "                                       \
 431                "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 432                "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 433                "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 434                "if test $? -ne 0; then "                               \
 435                        "echo OS PROGRAM FAILED; "                      \
 436                "else; "                                                \
 437                        "echo OS PROGRAM SUCCEEDED; "                   \
 438                "fi; "                                                  \
 439        "else; "                                                        \
 440                "echo OS DOWNLOAD FAILED; "                             \
 441        "fi;"
 442
 443#define CONFIG_PROG_FDT1                                                \
 444        "$download_cmd $fdtaddr $fdtfile; "                             \
 445        "if test $? -eq 0; then "                                       \
 446                "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 447                "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 448                "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 449                "if test $? -ne 0; then "                               \
 450                        "echo FDT PROGRAM FAILED; "                     \
 451                "else; "                                                \
 452                        "echo FDT PROGRAM SUCCEEDED; "                  \
 453                "fi; "                                                  \
 454        "else; "                                                        \
 455                "echo FDT DOWNLOAD FAILED; "                            \
 456        "fi;"
 457
 458#define CONFIG_PROG_FDT2                                                \
 459        "$download_cmd $fdtaddr $fdtfile; "                             \
 460        "if test $? -eq 0; then "                                       \
 461                "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 462                "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 463                "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 464                "if test $? -ne 0; then "                               \
 465                        "echo FDT PROGRAM FAILED; "                     \
 466                "else; "                                                \
 467                        "echo FDT PROGRAM SUCCEEDED; "                  \
 468                "fi; "                                                  \
 469        "else; "                                                        \
 470                "echo FDT DOWNLOAD FAILED; "                            \
 471        "fi;"
 472
 473#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 474        "autoload=yes\0"                                                \
 475        "download_cmd=tftp\0"                                           \
 476        "console_args=console=ttyS0,115200\0"                           \
 477        "root_args=root=/dev/nfs rw\0"                                  \
 478        "misc_args=ip=on\0"                                             \
 479        "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 480        "bootfile=/home/user/file\0"                                    \
 481        "osfile=/home/user/board.uImage\0"                              \
 482        "fdtfile=/home/user/board.dtb\0"                                \
 483        "ubootfile=/home/user/u-boot.bin\0"                             \
 484        "fdtaddr=0x1e00000\0"                                           \
 485        "osaddr=0x1000000\0"                                            \
 486        "loadaddr=0x1000000\0"                                          \
 487        "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 488        "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 489        "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 490        "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 491        "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 492        "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 493        "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 494        "bootcmd_flash1=run set_bootargs; "                             \
 495                "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 496        "bootcmd_flash2=run set_bootargs; "                             \
 497                "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 498        "bootcmd=run bootcmd_flash1\0"
 499#endif  /* __CONFIG_H */
 500