LXR uboot/arch/arm/mach-at91/arm926ejs/at91sam9rl

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007-2008
   4 * Stelian Pop <stelian@popies.net>
   5 * Lead Tech Design <www.leadtechdesign.com>
   6 */
   7
   8#include <common.h>
   9#include <asm/io.h>
  10#include <asm/arch/at91_common.h>
  11#include <asm/arch/clk.h>
  12#include <asm/arch/gpio.h>
  13
  14/*
  15 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
  16 * peripheral pins. Good to have if hardware is soldered optionally
  17 * or in case of SPI no slave is selected. Avoid lines to float
  18 * needlessly. Use a short local PUP define.
  19 *
  20 * Due to errata "TXD floats when CTS is inactive" pullups are always
  21 * on for TXD pins.
  22 */
  23#ifdef CONFIG_AT91_GPIO_PULLUP
  24# define PUP CONFIG_AT91_GPIO_PULLUP
  25#else
  26# define PUP 0
  27#endif
  28
  29void at91_serial0_hw_init(void)
  30{
  31        at91_set_a_periph(AT91_PIO_PORTA, 6, 1);                /* TXD0 */
  32        at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);              /* RXD0 */
  33        at91_periph_clk_enable(ATMEL_ID_USART0);
  34}
  35
  36void at91_serial1_hw_init(void)
  37{
  38        at91_set_a_periph(AT91_PIO_PORTA, 11, 1);               /* TXD1 */
  39        at91_set_a_periph(AT91_PIO_PORTA, 12, PUP);             /* RXD1 */
  40        at91_periph_clk_enable(ATMEL_ID_USART1);
  41}
  42
  43void at91_serial2_hw_init(void)
  44{
  45        at91_set_a_periph(AT91_PIO_PORTA, 13, 1);               /* TXD2 */
  46        at91_set_a_periph(AT91_PIO_PORTA, 14, PUP);             /* RXD2 */
  47        at91_periph_clk_enable(ATMEL_ID_USART2);
  48}
  49
  50void at91_seriald_hw_init(void)
  51{
  52        at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);             /* DRXD */
  53        at91_set_a_periph(AT91_PIO_PORTA, 22, 1);               /* DTXD */
  54        at91_periph_clk_enable(ATMEL_ID_SYS);
  55}
  56
  57#ifdef CONFIG_ATMEL_SPI
  58void at91_spi0_hw_init(unsigned long cs_mask)
  59{
  60        at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);     /* SPI0_MISO */
  61        at91_set_a_periph(AT91_PIO_PORTA, 26, PUP);     /* SPI0_MOSI */
  62        at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);     /* SPI0_SPCK */
  63
  64        at91_periph_clk_enable(ATMEL_ID_SPI);
  65
  66        if (cs_mask & (1 << 0)) {
  67                at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
  68        }
  69        if (cs_mask & (1 << 1)) {
  70                at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
  71        }
  72        if (cs_mask & (1 << 2)) {
  73                at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
  74        }
  75        if (cs_mask & (1 << 3)) {
  76                at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
  77        }
  78        if (cs_mask & (1 << 4)) {
  79                at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
  80        }
  81        if (cs_mask & (1 << 5)) {
  82                at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
  83        }
  84        if (cs_mask & (1 << 6)) {
  85                at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
  86        }
  87        if (cs_mask & (1 << 7)) {
  88                at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
  89        }
  90}
  91#endif
  92
  93#ifdef CONFIG_GENERIC_ATMEL_MCI
  94void at91_mci_hw_init(void)
  95{
  96        at91_set_a_periph(AT91_PIO_PORTA, 2, 0);        /* MCI CLK */
  97        at91_set_a_periph(AT91_PIO_PORTA, 1, 0);        /* MCI CDA */
  98        at91_set_a_periph(AT91_PIO_PORTA, 0, 0);        /* MCI DA0 */
  99        at91_set_a_periph(AT91_PIO_PORTA, 3, 0);        /* MCI DA1 */
 100        at91_set_a_periph(AT91_PIO_PORTA, 4, 0);        /* MCI DA2 */
 101        at91_set_a_periph(AT91_PIO_PORTA, 5, 0);        /* MCI DA3 */
 102
 103        at91_periph_clk_enable(ATMEL_ID_MCI);
 104}
 105#endif
 106