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13#include <asm/emif.h>
14#include <asm/arch/sys_proto.h>
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33#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
34const struct emif_regs emif_regs_532_mhz_2cs = {
35 .sdram_config_init = 0x80800EBA,
36 .sdram_config = 0x808022BA,
37 .ref_ctrl = 0x0000081A,
38 .sdram_tim1 = 0x772F6873,
39 .sdram_tim2 = 0x304a129a,
40 .sdram_tim3 = 0x02f7e45f,
41 .read_idle_ctrl = 0x00050000,
42 .zq_config = 0x000b3215,
43 .temp_alert_config = 0x08000a05,
44 .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
45 .emif_ddr_phy_ctlr_1 = 0x0E28420d,
46 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
47 .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
48 .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
49 .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
50 .emif_ddr_ext_phy_ctrl_5 = 0x04010040
51};
52
53const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
54 .sdram_config_init = 0x80800EBA,
55 .sdram_config = 0x808022BA,
56 .ref_ctrl = 0x0000081A,
57 .sdram_tim1 = 0x772F6873,
58 .sdram_tim2 = 0x304a129a,
59 .sdram_tim3 = 0x02f7e45f,
60 .read_idle_ctrl = 0x00050000,
61 .zq_config = 0x100b3215,
62 .temp_alert_config = 0x08000a05,
63 .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
64 .emif_ddr_phy_ctlr_1 = 0x0E30400d,
65 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
66 .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
67 .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
68 .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
69 .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
70};
71
72const struct emif_regs emif_regs_266_mhz_2cs = {
73 .sdram_config_init = 0x80800EBA,
74 .sdram_config = 0x808022BA,
75 .ref_ctrl = 0x0000040D,
76 .sdram_tim1 = 0x2A86B419,
77 .sdram_tim2 = 0x1025094A,
78 .sdram_tim3 = 0x026BA22F,
79 .read_idle_ctrl = 0x00050000,
80 .zq_config = 0x000b3215,
81 .temp_alert_config = 0x08000a05,
82 .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
83 .emif_ddr_phy_ctlr_1 = 0x0E28420d,
84 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
85 .emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
86 .emif_ddr_ext_phy_ctrl_3 = 0x14829052,
87 .emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
88 .emif_ddr_ext_phy_ctrl_5 = 0x04010040
89};
90
91const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
92 .sdram_config_init = 0x61851B32,
93 .sdram_config = 0x61851B32,
94 .sdram_config2 = 0x0,
95 .ref_ctrl = 0x00001035,
96 .sdram_tim1 = 0xCCCF36B3,
97 .sdram_tim2 = 0x308F7FDA,
98 .sdram_tim3 = 0x027F88A8,
99 .read_idle_ctrl = 0x00050000,
100 .zq_config = 0x0007190B,
101 .temp_alert_config = 0x00000000,
102 .emif_ddr_phy_ctlr_1_init = 0x0020420A,
103 .emif_ddr_phy_ctlr_1 = 0x0024420A,
104 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
105 .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
106 .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
107 .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
108 .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
109 .emif_rd_wr_lvl_rmp_win = 0x00000000,
110 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
111 .emif_rd_wr_lvl_ctl = 0x00000000,
112 .emif_rd_wr_exec_thresh = 0x00000305
113};
114
115const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
116 .sdram_config_init = 0x61851B32,
117 .sdram_config = 0x61851B32,
118 .sdram_config2 = 0x0,
119 .ref_ctrl = 0x00001035,
120 .sdram_tim1 = 0xCCCF36B3,
121 .sdram_tim2 = 0x308F7FDA,
122 .sdram_tim3 = 0x027F88A8,
123 .read_idle_ctrl = 0x00050000,
124 .zq_config = 0x1007190B,
125 .temp_alert_config = 0x00000000,
126 .emif_ddr_phy_ctlr_1_init = 0x0030400A,
127 .emif_ddr_phy_ctlr_1 = 0x0034400A,
128 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
129 .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
130 .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
131 .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
132 .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
133 .emif_rd_wr_lvl_rmp_win = 0x00000000,
134 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
135 .emif_rd_wr_lvl_ctl = 0x00000000,
136 .emif_rd_wr_exec_thresh = 0x40000305
137};
138
139const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
140 .dmm_lisa_map_0 = 0x0,
141 .dmm_lisa_map_1 = 0x0,
142 .dmm_lisa_map_2 = 0x80740300,
143 .dmm_lisa_map_3 = 0xFF020100,
144 .is_ma_present = 0x1
145};
146
147static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
148{
149 switch (omap_revision()) {
150 case OMAP5430_ES1_0:
151 *regs = &emif_regs_532_mhz_2cs;
152 break;
153 case OMAP5432_ES1_0:
154 *regs = &emif_regs_ddr3_532_mhz_1cs;
155 break;
156 case OMAP5430_ES2_0:
157 *regs = &emif_regs_532_mhz_2cs_es2;
158 break;
159 case OMAP5432_ES2_0:
160 default:
161 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
162 break;
163 }
164}
165
166void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
167 __attribute__((weak, alias("emif_get_reg_dump_sdp")));
168
169static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
170 **dmm_lisa_regs)
171{
172 switch (omap_revision()) {
173 case OMAP5430_ES1_0:
174 case OMAP5430_ES2_0:
175 case OMAP5432_ES1_0:
176 case OMAP5432_ES2_0:
177 default:
178 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
179 break;
180 }
181
182}
183
184void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
185 __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
186#else
187
188static const struct lpddr2_device_details dev_4G_S4_details = {
189 .type = LPDDR2_TYPE_S4,
190 .density = LPDDR2_DENSITY_4Gb,
191 .io_width = LPDDR2_IO_WIDTH_32,
192 .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
193};
194
195static void emif_get_device_details_sdp(u32 emif_nr,
196 struct lpddr2_device_details *cs0_device_details,
197 struct lpddr2_device_details *cs1_device_details)
198{
199
200 *cs0_device_details = dev_4G_S4_details;
201 *cs1_device_details = dev_4G_S4_details;
202}
203
204void emif_get_device_details(u32 emif_nr,
205 struct lpddr2_device_details *cs0_device_details,
206 struct lpddr2_device_details *cs1_device_details)
207 __attribute__((weak, alias("emif_get_device_details_sdp")));
208
209#endif
210
211const u32 ext_phy_ctrl_const_base[] = {
212 0x01004010,
213 0x00001004,
214 0x04010040,
215 0x01004010,
216 0x00001004,
217 0x00000000,
218 0x00000000,
219 0x00000000,
220 0x80080080,
221 0x00800800,
222 0x08102040,
223 0x00000001,
224 0x540A8150,
225 0xA81502a0,
226 0x002A0540,
227 0x00000000,
228 0x00000000,
229 0x00000000,
230 0x00000077,
231 0x0
232};
233
234const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
235 0x01004010,
236 0x00001004,
237 0x04010040,
238 0x01004010,
239 0x00001004,
240 0x00000000,
241 0x00000000,
242 0x00000000,
243 0x80080080,
244 0x00800800,
245 0x08102040,
246 0x00000002,
247 0x0,
248 0x0,
249 0x0,
250 0x00000000,
251 0x00000000,
252 0x00000000,
253 0x00000057,
254 0x0
255};
256
257const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
258 0x50D4350D,
259 0x00000D43,
260 0x04010040,
261 0x01004010,
262 0x00001004,
263 0x00000000,
264 0x00000000,
265 0x00000000,
266 0x80080080,
267 0x00800800,
268 0x08102040,
269 0x00000002,
270 0x00000000,
271 0x00000000,
272 0x00000000,
273 0x00000000,
274 0x00000000,
275 0x00000000,
276 0x00000057,
277 0x0
278};
279
280
281const u32
282dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
283 0x10040100,
284 0x00910091,
285 0x00950095,
286 0x009B009B,
287 0x009E009E,
288 0x00980098,
289 0x00340034,
290 0x00350035,
291 0x00340034,
292 0x00310031,
293 0x00340034,
294 0x007F007F,
295 0x007F007F,
296 0x007F007F,
297 0x007F007F,
298 0x007F007F,
299 0x00480048,
300 0x004A004A,
301 0x00520052,
302 0x00550055,
303 0x00500050,
304 0x00000000,
305 0x00600020,
306 0x40011080,
307 0x08102040,
308 0x0,
309 0x0,
310 0x0,
311 0x0,
312 0x0,
313 0x0,
314 0x0,
315 0x0,
316 0x0,
317 0x0
318};
319
320
321const u32
322dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
323 0x10040100,
324 0x00910091,
325 0x00950095,
326 0x009B009B,
327 0x009E009E,
328 0x00980098,
329 0x00330033,
330 0x00330033,
331 0x002F002F,
332 0x00320032,
333 0x00310031,
334 0x007F007F,
335 0x007F007F,
336 0x007F007F,
337 0x007F007F,
338 0x007F007F,
339 0x00520052,
340 0x00520052,
341 0x00470047,
342 0x00490049,
343 0x00500050,
344 0x00000000,
345 0x00600020,
346 0x40011080,
347 0x08102040,
348 0x0,
349 0x0,
350 0x0,
351 0x0,
352 0x0,
353 0x0,
354 0x0,
355 0x0,
356 0x0,
357 0x0
358};
359
360
361const u32
362dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
363 0x10040100,
364 0x00A400A4,
365 0x00A900A9,
366 0x00B000B0,
367 0x00B000B0,
368 0x00A400A4,
369 0x00390039,
370 0x00320032,
371 0x00320032,
372 0x00320032,
373 0x00440044,
374 0x00550055,
375 0x00550055,
376 0x00550055,
377 0x00550055,
378 0x007F007F,
379 0x004D004D,
380 0x00430043,
381 0x00560056,
382 0x00540054,
383 0x00600060,
384 0x0,
385 0x00600020,
386 0x40010080,
387 0x08102040,
388 0x0,
389 0x0,
390 0x0,
391 0x0,
392 0x0,
393 0x0,
394 0x0,
395 0x0,
396 0x0,
397 0x0
398};
399
400const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
401 0x04040100,
402 0x006B009F,
403 0x006B00A2,
404 0x006B00A8,
405 0x006B00A8,
406 0x006B00B2,
407 0x002F002F,
408 0x002F002F,
409 0x002F002F,
410 0x002F002F,
411 0x002F002F,
412 0x00600073,
413 0x00600071,
414 0x0060007C,
415 0x0060007E,
416 0x00600084,
417 0x00400053,
418 0x00400051,
419 0x0040005C,
420 0x0040005E,
421 0x00400064,
422 0x00800080,
423 0x00800080,
424 0x40010080,
425 0x08102040,
426 0x005B008F,
427 0x005B0092,
428 0x005B0098,
429 0x005B0098,
430 0x005B00A2,
431 0x00300043,
432 0x00300041,
433 0x0030004C,
434 0x0030004E,
435 0x00300054,
436 0x00000077
437};
438
439const struct lpddr2_mr_regs mr_regs = {
440 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
441 .mr2 = 0x6,
442 .mr3 = 0x1,
443 .mr10 = MR10_ZQ_ZQINIT,
444 .mr16 = MR16_REF_FULL_ARRAY
445};
446
447void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
448 const u32 **regs,
449 u32 *size)
450{
451 switch (omap_revision()) {
452 case OMAP5430_ES1_0:
453 case OMAP5430_ES2_0:
454 *regs = ext_phy_ctrl_const_base;
455 *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
456 break;
457 case OMAP5432_ES1_0:
458 *regs = ddr3_ext_phy_ctrl_const_base_es1;
459 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
460 break;
461 case OMAP5432_ES2_0:
462 *regs = ddr3_ext_phy_ctrl_const_base_es2;
463 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
464 break;
465 case DRA752_ES1_0:
466 case DRA752_ES1_1:
467 case DRA752_ES2_0:
468 if (emif_nr == 1) {
469 *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
470 *size =
471 ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
472 } else {
473 *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
474 *size =
475 ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
476 }
477 break;
478 case DRA722_ES1_0:
479 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
480 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
481 break;
482 case DRA762_ES1_0:
483 case DRA762_ABZ_ES1_0:
484 case DRA762_ACD_ES1_0:
485 case DRA722_ES2_0:
486 case DRA722_ES2_1:
487 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
488 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
489 break;
490 default:
491 *regs = ddr3_ext_phy_ctrl_const_base_es2;
492 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
493
494 }
495}
496
497void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
498{
499 *regs = &mr_regs;
500}
501
502static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
503{
504 u32 *ext_phy_ctrl_base = 0;
505 u32 *emif_ext_phy_ctrl_base = 0;
506 u32 emif_nr;
507 const u32 *ext_phy_ctrl_const_regs;
508 u32 i = 0;
509 u32 size;
510
511 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
512
513 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
514
515 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
516 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
517
518
519 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
520 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
521
522 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
523 }
524
525
526
527
528
529 emif_get_ext_phy_ctrl_const_regs(emif_nr,
530 &ext_phy_ctrl_const_regs, &size);
531
532 for (i = 0; i < size; i++) {
533 writel(ext_phy_ctrl_const_regs[i],
534 emif_ext_phy_ctrl_base++);
535
536 writel(ext_phy_ctrl_const_regs[i],
537 emif_ext_phy_ctrl_base++);
538 }
539}
540
541static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
542{
543 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
544 u32 *emif_ext_phy_ctrl_base = 0;
545 u32 emif_nr;
546 const u32 *ext_phy_ctrl_const_regs;
547 u32 i, hw_leveling, size, phy;
548
549 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
550
551 hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
552 phy = regs->emif_ddr_phy_ctlr_1_init;
553
554 emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
555
556 emif_get_ext_phy_ctrl_const_regs(emif_nr,
557 &ext_phy_ctrl_const_regs, &size);
558
559 writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
560 writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
561
562
563
564
565
566 if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
567 for (i = 1; i < 6; i++) {
568 writel(ext_phy_ctrl_const_regs[i],
569 &emif_ext_phy_ctrl_base[i * 2]);
570 writel(ext_phy_ctrl_const_regs[i],
571 &emif_ext_phy_ctrl_base[i * 2 + 1]);
572 }
573
574 if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
575 for (i = 6; i < 11; i++) {
576 writel(ext_phy_ctrl_const_regs[i],
577 &emif_ext_phy_ctrl_base[i * 2]);
578 writel(ext_phy_ctrl_const_regs[i],
579 &emif_ext_phy_ctrl_base[i * 2 + 1]);
580 }
581
582 if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
583 for (i = 11; i < 25; i++) {
584 writel(ext_phy_ctrl_const_regs[i],
585 &emif_ext_phy_ctrl_base[i * 2]);
586 writel(ext_phy_ctrl_const_regs[i],
587 &emif_ext_phy_ctrl_base[i * 2 + 1]);
588 }
589
590 if (hw_leveling) {
591
592
593
594 for (i = 21; i < 35; i++) {
595 writel(ext_phy_ctrl_const_regs[i],
596 &emif_ext_phy_ctrl_base[i * 2]);
597 writel(ext_phy_ctrl_const_regs[i],
598 &emif_ext_phy_ctrl_base[i * 2 + 1]);
599 }
600 }
601}
602
603void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
604{
605 if (is_omap54xx())
606 do_ext_phy_settings_omap5(base, regs);
607 else
608 do_ext_phy_settings_dra7(base, regs);
609}
610
611#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
612static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
613 .max_freq = 532000000,
614 .RL = 8,
615 .tRPab = 21,
616 .tRCD = 18,
617 .tWR = 15,
618 .tRASmin = 42,
619 .tRRD = 10,
620 .tWTRx2 = 15,
621 .tXSR = 140,
622 .tXPx2 = 15,
623 .tRFCab = 130,
624 .tRTPx2 = 15,
625 .tCKE = 3,
626 .tCKESR = 15,
627 .tZQCS = 90,
628 .tZQCL = 360,
629 .tZQINIT = 1000,
630 .tDQSCKMAXx2 = 11,
631 .tRASmax = 70,
632 .tFAW = 50
633};
634
635static const struct lpddr2_min_tck min_tck = {
636 .tRL = 3,
637 .tRP_AB = 3,
638 .tRCD = 3,
639 .tWR = 3,
640 .tRAS_MIN = 3,
641 .tRRD = 2,
642 .tWTR = 2,
643 .tXP = 2,
644 .tRTP = 2,
645 .tCKE = 3,
646 .tCKESR = 3,
647 .tFAW = 8
648};
649
650static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
651 &timings_jedec_532_mhz
652};
653
654static const struct lpddr2_device_timings dev_4G_S4_timings = {
655 .ac_timings = ac_timings,
656 .min_tck = &min_tck,
657};
658
659
660
661
662
663
664const struct read_write_regs omap5_bug_00339_regs[] = {
665 { 8, 5 },
666 { 9, 6 },
667 { 10, 7 },
668 { 14, 8 },
669 { 15, 9 },
670 { 16, 10 },
671 { 11, 2 },
672 { 12, 3 },
673 { 13, 4 },
674 { 17, 11 },
675 { 18, 12 },
676 { 19, 13 },
677};
678
679const struct read_write_regs dra_bug_00339_regs[] = {
680 { 7, 7 },
681 { 8, 8 },
682 { 9, 9 },
683 { 10, 10 },
684 { 11, 11 },
685 { 12, 2 },
686 { 13, 3 },
687 { 14, 4 },
688 { 15, 5 },
689 { 16, 6 },
690 { 17, 12 },
691 { 18, 13 },
692 { 19, 14 },
693 { 20, 15 },
694 { 21, 16 },
695 { 22, 17 },
696 { 23, 18 },
697 { 24, 19 },
698 { 25, 20 },
699 { 26, 21}
700};
701
702const struct read_write_regs *get_bug_regs(u32 *iterations)
703{
704 const struct read_write_regs *bug_00339_regs_ptr = NULL;
705
706 switch (omap_revision()) {
707 case OMAP5430_ES1_0:
708 case OMAP5430_ES2_0:
709 case OMAP5432_ES1_0:
710 case OMAP5432_ES2_0:
711 bug_00339_regs_ptr = omap5_bug_00339_regs;
712 *iterations = sizeof(omap5_bug_00339_regs)/
713 sizeof(omap5_bug_00339_regs[0]);
714 break;
715 case DRA762_ABZ_ES1_0:
716 case DRA762_ACD_ES1_0:
717 case DRA762_ES1_0:
718 case DRA752_ES1_0:
719 case DRA752_ES1_1:
720 case DRA752_ES2_0:
721 case DRA722_ES1_0:
722 case DRA722_ES2_0:
723 case DRA722_ES2_1:
724 bug_00339_regs_ptr = dra_bug_00339_regs;
725 *iterations = sizeof(dra_bug_00339_regs)/
726 sizeof(dra_bug_00339_regs[0]);
727 break;
728 default:
729 printf("\n Error: UnKnown SOC");
730 }
731
732 return bug_00339_regs_ptr;
733}
734
735void emif_get_device_timings_sdp(u32 emif_nr,
736 const struct lpddr2_device_timings **cs0_device_timings,
737 const struct lpddr2_device_timings **cs1_device_timings)
738{
739
740 *cs0_device_timings = &dev_4G_S4_timings;
741 *cs1_device_timings = &dev_4G_S4_timings;
742}
743
744void emif_get_device_timings(u32 emif_nr,
745 const struct lpddr2_device_timings **cs0_device_timings,
746 const struct lpddr2_device_timings **cs1_device_timings)
747 __attribute__((weak, alias("emif_get_device_timings_sdp")));
748
749#endif
750
