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7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/at91_common.h>
10#include <asm/arch/at91_rstc.h>
11#include <asm/arch/atmel_mpddrc.h>
12#include <asm/arch/gpio.h>
13#include <asm/arch/clk.h>
14#include <asm/arch/sama5d3_smc.h>
15#include <asm/arch/sama5d4.h>
16#include <debug_uart.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20extern void at91_pda_detect(void);
21
22#ifdef CONFIG_NAND_ATMEL
23static void sama5d4_xplained_nand_hw_init(void)
24{
25 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
26
27 at91_periph_clk_enable(ATMEL_ID_SMC);
28
29
30 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
31 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
32 &smc->cs[3].setup);
33 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
34 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
35 &smc->cs[3].pulse);
36 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
37 &smc->cs[3].cycle);
38 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
39 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
40 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
41 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
42 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
43 AT91_SMC_MODE_EXNW_DISABLE |
44 AT91_SMC_MODE_DBW_8 |
45 AT91_SMC_MODE_TDF_CYCLE(3),
46 &smc->cs[3].mode);
47
48 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);
49 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);
50 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);
51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);
52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);
53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);
54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);
55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);
56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);
57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);
58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);
59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);
60 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);
61 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);
62}
63#endif
64
65#ifdef CONFIG_CMD_USB
66static void sama5d4_xplained_usb_hw_init(void)
67{
68 at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
69 at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
70}
71#endif
72
73#ifdef CONFIG_BOARD_LATE_INIT
74int board_late_init(void)
75{
76 at91_pda_detect();
77#ifdef CONFIG_DM_VIDEO
78 at91_video_show_board_info();
79#endif
80 return 0;
81}
82#endif
83
84#ifdef CONFIG_DEBUG_UART_BOARD_INIT
85static void sama5d4_xplained_serial3_hw_init(void)
86{
87 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);
88 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);
89
90
91 at91_periph_clk_enable(ATMEL_ID_USART3);
92}
93
94void board_debug_uart_init(void)
95{
96 sama5d4_xplained_serial3_hw_init();
97}
98#endif
99
100#ifdef CONFIG_BOARD_EARLY_INIT_F
101int board_early_init_f(void)
102{
103#ifdef CONFIG_DEBUG_UART
104 debug_uart_init();
105#endif
106 return 0;
107}
108#endif
109
110#define AT24MAC_MAC_OFFSET 0x9a
111
112#ifdef CONFIG_MISC_INIT_R
113int misc_init_r(void)
114{
115#ifdef CONFIG_I2C_EEPROM
116 at91_set_ethaddr(AT24MAC_MAC_OFFSET);
117#endif
118 return 0;
119}
120#endif
121
122int board_init(void)
123{
124
125 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
126
127#ifdef CONFIG_NAND_ATMEL
128 sama5d4_xplained_nand_hw_init();
129#endif
130#ifdef CONFIG_CMD_USB
131 sama5d4_xplained_usb_hw_init();
132#endif
133
134 return 0;
135}
136
137int dram_init(void)
138{
139 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
140 CONFIG_SYS_SDRAM_SIZE);
141 return 0;
142}
143
144
145#ifdef CONFIG_SPL_BUILD
146void spl_board_init(void)
147{
148#if CONFIG_NAND_BOOT
149 sama5d4_xplained_nand_hw_init();
150#endif
151}
152
153static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
154{
155 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
156
157 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
158 ATMEL_MPDDRC_CR_NR_ROW_14 |
159 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
160 ATMEL_MPDDRC_CR_NB_8BANKS |
161 ATMEL_MPDDRC_CR_NDQS_DISABLED |
162 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
163 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
164
165 ddr2->rtr = 0x2b0;
166
167 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
168 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
169 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
170 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
171 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
172 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
173 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
174 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
175
176 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
177 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
178 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
179 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
180
181 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
182 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
183 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
184 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
185 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
186}
187
188void mem_init(void)
189{
190 struct atmel_mpddrc_config ddr2;
191
192 ddr2_conf(&ddr2);
193
194
195 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
196 at91_system_clk_enable(AT91_PMC_DDR);
197
198
199 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
200}
201
202void at91_pmc_init(void)
203{
204 u32 tmp;
205
206 tmp = AT91_PMC_PLLAR_29 |
207 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
208 AT91_PMC_PLLXR_MUL(87) |
209 AT91_PMC_PLLXR_DIV(1);
210 at91_plla_init(tmp);
211
212 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
213
214 tmp = AT91_PMC_MCKR_H32MXDIV |
215 AT91_PMC_MCKR_PLLADIV_2 |
216 AT91_PMC_MCKR_MDIV_3 |
217 AT91_PMC_MCKR_CSS_PLLA;
218 at91_mck_init(tmp);
219}
220#endif
221
