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8#include <asm/arch/clock.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/iomux.h>
11#include <asm/arch/mx6-pins.h>
12#include <env.h>
13#include <linux/errno.h>
14#include <asm/gpio.h>
15#include <asm/mach-imx/mxc_i2c.h>
16#include <asm/mach-imx/iomux-v3.h>
17#include <asm/mach-imx/boot_mode.h>
18#include <asm/mach-imx/video.h>
19#include <mmc.h>
20#include <fsl_esdhc_imx.h>
21#include <miiphy.h>
22#include <netdev.h>
23#include <asm/arch/mxc_hdmi.h>
24#include <asm/arch/crm_regs.h>
25#include <asm/io.h>
26#include <asm/arch/sys_proto.h>
27#include <i2c.h>
28#include <input.h>
29#include <power/pmic.h>
30#include <power/pfuze100_pmic.h>
31#include <asm/arch/mx6-ddr.h>
32
33DECLARE_GLOBAL_DATA_PTR;
34
35#define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12))
36
37#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
45#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47
48#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
50
51#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
53
54#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
56
57#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
58 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
59 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
60
61#define I2C_PMIC 1
62
63#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
64
65#define ETH_PHY_RESET IMX_GPIO_NR(2, 4)
66
67int dram_init(void)
68{
69 gd->ram_size = imx_ddr_size();
70
71 return 0;
72}
73
74iomux_v3_cfg_t const uart2_pads[] = {
75 MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
76 MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77};
78
79static void setup_iomux_uart(void)
80{
81 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
82}
83
84#ifdef CONFIG_TARGET_ZC5202
85iomux_v3_cfg_t const enet_pads[] = {
86 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
93 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
100
101 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
102
103 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
104
105 MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
106 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
107
108};
109
110#define BOARD_NAME "EL6x-ZC5202"
111#else
112iomux_v3_cfg_t const enet_pads[] = {
113 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
122 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
126 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
127 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
128 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
129 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
130};
131#define BOARD_NAME "EL6x-ZC5601"
132#endif
133
134static void setup_iomux_enet(void)
135{
136 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
137
138#ifdef CONFIG_TARGET_ZC5202
139
140 gpio_direction_input(IMX_GPIO_NR(4, 9));
141 gpio_direction_input(IMX_GPIO_NR(4, 12));
142
143
144 gpio_direction_output(ETH_PHY_RESET , 0);
145 mdelay(2);
146 gpio_set_value(ETH_PHY_RESET, 1);
147#endif
148}
149
150int board_phy_config(struct phy_device *phydev)
151{
152 if (phydev->drv->config)
153 phydev->drv->config(phydev);
154
155 return 0;
156}
157
158#ifdef CONFIG_MXC_SPI
159#ifdef CONFIG_TARGET_ZC5202
160iomux_v3_cfg_t const ecspi1_pads[] = {
161 MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
162 MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
163 MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
164 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
165 MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
166};
167
168iomux_v3_cfg_t const ecspi3_pads[] = {
169 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
170 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
171 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
172 MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL),
173 MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL),
174 MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
175 MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL),
176};
177#endif
178
179iomux_v3_cfg_t const ecspi4_pads[] = {
180 MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
181 MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
182 MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
183 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
184};
185
186int board_spi_cs_gpio(unsigned bus, unsigned cs)
187{
188 return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
189 ? (IMX_GPIO_NR(3, 20)) : -1;
190}
191
192static void setup_spi(void)
193{
194#ifdef CONFIG_TARGET_ZC5202
195 gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
196 gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
197 gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
198 gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
199 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
200#endif
201
202 gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
203 gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
204 imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
205
206 enable_spi_clk(true, 3);
207}
208#endif
209
210static struct i2c_pads_info i2c_pad_info1 = {
211 .scl = {
212 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
213 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
214 .gp = IMX_GPIO_NR(2, 30)
215 },
216 .sda = {
217 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
218 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
219 .gp = IMX_GPIO_NR(4, 13)
220 }
221};
222
223static struct i2c_pads_info i2c_pad_info2 = {
224 .scl = {
225 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
226 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
227 .gp = IMX_GPIO_NR(1, 5)
228 },
229 .sda = {
230 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
231 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
232 .gp = IMX_GPIO_NR(7, 11)
233 }
234};
235
236iomux_v3_cfg_t const usdhc2_pads[] = {
237 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
238 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
239 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
240 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
241 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
242 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
243 MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL),
244};
245
246iomux_v3_cfg_t const usdhc4_pads[] = {
247 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
248 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
249 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
250 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
251 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
252 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257};
258
259#ifdef CONFIG_FSL_ESDHC_IMX
260struct fsl_esdhc_cfg usdhc_cfg[2] = {
261 {USDHC2_BASE_ADDR},
262 {USDHC4_BASE_ADDR},
263};
264
265#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
266
267int board_mmc_getcd(struct mmc *mmc)
268{
269 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
270 int ret = 0;
271
272 switch (cfg->esdhc_base) {
273 case USDHC2_BASE_ADDR:
274 ret = !gpio_get_value(USDHC2_CD_GPIO);
275 break;
276 case USDHC4_BASE_ADDR:
277 ret = 1;
278 break;
279 }
280
281 return ret;
282}
283
284int board_mmc_init(bd_t *bis)
285{
286#ifndef CONFIG_SPL_BUILD
287 int ret;
288 int i;
289
290
291
292
293
294
295
296
297 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
298 switch (i) {
299 case 0:
300 imx_iomux_v3_setup_multiple_pads(
301 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
302 gpio_direction_input(USDHC2_CD_GPIO);
303 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
304 break;
305 case 1:
306 imx_iomux_v3_setup_multiple_pads(
307 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
308 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
309 break;
310 default:
311 printf("Warning: you configured more USDHC controllers"
312 "(%d) then supported by the board (%d)\n",
313 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
314 return -EINVAL;
315 }
316
317 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
318 if (ret)
319 return ret;
320 }
321
322 return 0;
323#else
324 struct src *psrc = (struct src *)SRC_BASE_ADDR;
325 unsigned reg = readl(&psrc->sbmr1) >> 11;
326
327
328
329
330
331
332
333
334
335
336 switch (reg & 0x3) {
337 case 0x1:
338 imx_iomux_v3_setup_multiple_pads(
339 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
340 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
341 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
342 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
343 break;
344 case 0x3:
345 imx_iomux_v3_setup_multiple_pads(
346 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
347 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
348 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
349 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
350 break;
351 }
352
353 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
354#endif
355
356}
357#endif
358
359
360
361
362
363
364int overwrite_console(void)
365{
366 return 1;
367}
368
369int board_eth_init(bd_t *bis)
370{
371 setup_iomux_enet();
372 enable_enet_clk(1);
373
374 return cpu_eth_init(bis);
375}
376
377int board_early_init_f(void)
378{
379
380 setup_iomux_uart();
381 setup_spi();
382
383 return 0;
384}
385
386int board_init(void)
387{
388
389 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
390
391 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
392 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
393
394 return 0;
395}
396
397int power_init_board(void)
398{
399 struct pmic *p;
400 int ret;
401 unsigned int reg;
402
403 ret = power_pfuze100_init(I2C_PMIC);
404 if (ret)
405 return ret;
406
407 p = pmic_get("PFUZE100");
408 ret = pmic_probe(p);
409 if (ret)
410 return ret;
411
412 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
413 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
414
415
416 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
417 reg &= ~LDO_VOL_MASK;
418 reg |= LDOB_2_80V;
419 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
420
421
422 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
423 reg &= ~LDO_VOL_MASK;
424 reg |= LDOB_3_00V;
425 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
426
427
428 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
429 reg &= ~SW1x_STBY_MASK;
430 reg |= SW1x_0_975V;
431 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
432
433
434 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
435 reg &= ~SW1xCONF_DVSSPEED_MASK;
436 reg |= SW1xCONF_DVSSPEED_4US;
437 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
438
439
440 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
441 reg &= ~SW1x_STBY_MASK;
442 reg |= SW1x_0_975V;
443 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
444
445
446 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
447 reg &= ~SW1xCONF_DVSSPEED_MASK;
448 reg |= SW1xCONF_DVSSPEED_4US;
449 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
450
451 return 0;
452}
453
454#ifdef CONFIG_CMD_BMODE
455static const struct boot_mode board_boot_modes[] = {
456
457 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
458
459 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
460 {NULL, 0},
461};
462#endif
463
464int board_late_init(void)
465{
466#ifdef CONFIG_CMD_BMODE
467 add_board_boot_modes(board_boot_modes);
468#endif
469
470 env_set("board_name", BOARD_NAME);
471 return 0;
472}
473
474int checkboard(void)
475{
476 puts("Board: ");
477 puts(BOARD_NAME "\n");
478
479 return 0;
480}
481
482#ifdef CONFIG_SPL_BUILD
483#include <spl.h>
484#include <linux/libfdt.h>
485
486const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
487 .dram_sdclk_0 = 0x00020030,
488 .dram_sdclk_1 = 0x00020030,
489 .dram_cas = 0x00020030,
490 .dram_ras = 0x00020030,
491 .dram_reset = 0x00020030,
492 .dram_sdcke0 = 0x00003000,
493 .dram_sdcke1 = 0x00003000,
494 .dram_sdba2 = 0x00000000,
495 .dram_sdodt0 = 0x00003030,
496 .dram_sdodt1 = 0x00003030,
497 .dram_sdqs0 = 0x00000030,
498 .dram_sdqs1 = 0x00000030,
499 .dram_sdqs2 = 0x00000030,
500 .dram_sdqs3 = 0x00000030,
501 .dram_sdqs4 = 0x00000030,
502 .dram_sdqs5 = 0x00000030,
503 .dram_sdqs6 = 0x00000030,
504 .dram_sdqs7 = 0x00000030,
505 .dram_dqm0 = 0x00020030,
506 .dram_dqm1 = 0x00020030,
507 .dram_dqm2 = 0x00020030,
508 .dram_dqm3 = 0x00020030,
509 .dram_dqm4 = 0x00020030,
510 .dram_dqm5 = 0x00020030,
511 .dram_dqm6 = 0x00020030,
512 .dram_dqm7 = 0x00020030,
513};
514
515const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
516 .grp_ddr_type = 0x000C0000,
517 .grp_ddrmode_ctl = 0x00020000,
518 .grp_ddrpke = 0x00000000,
519 .grp_addds = 0x00000030,
520 .grp_ctlds = 0x00000030,
521 .grp_ddrmode = 0x00020000,
522 .grp_b0ds = 0x00000030,
523 .grp_b1ds = 0x00000030,
524 .grp_b2ds = 0x00000030,
525 .grp_b3ds = 0x00000030,
526 .grp_b4ds = 0x00000030,
527 .grp_b5ds = 0x00000030,
528 .grp_b6ds = 0x00000030,
529 .grp_b7ds = 0x00000030,
530};
531
532const struct mx6_mmdc_calibration mx6_mmcd_calib = {
533 .p0_mpwldectrl0 = 0x001F001F,
534 .p0_mpwldectrl1 = 0x001F001F,
535 .p1_mpwldectrl0 = 0x00440044,
536 .p1_mpwldectrl1 = 0x00440044,
537 .p0_mpdgctrl0 = 0x434B0350,
538 .p0_mpdgctrl1 = 0x034C0359,
539 .p1_mpdgctrl0 = 0x434B0350,
540 .p1_mpdgctrl1 = 0x03650348,
541 .p0_mprddlctl = 0x4436383B,
542 .p1_mprddlctl = 0x39393341,
543 .p0_mpwrdlctl = 0x35373933,
544 .p1_mpwrdlctl = 0x48254A36,
545};
546
547
548static struct mx6_ddr3_cfg mem_ddr = {
549 .mem_speed = 1600,
550 .density = 2,
551 .width = 16,
552 .banks = 8,
553 .rowaddr = 14,
554 .coladdr = 10,
555 .pagesz = 2,
556 .trcd = 1375,
557 .trcmin = 4875,
558 .trasmin = 3500,
559};
560
561static void ccgr_init(void)
562{
563 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
564
565 writel(0x00C03F3F, &ccm->CCGR0);
566 writel(0x0030FC03, &ccm->CCGR1);
567 writel(0x0FFFC000, &ccm->CCGR2);
568 writel(0x3FF00000, &ccm->CCGR3);
569 writel(0x00FFF300, &ccm->CCGR4);
570 writel(0x0F0000C3, &ccm->CCGR5);
571 writel(0x000003FF, &ccm->CCGR6);
572}
573
574
575
576
577
578static void spl_dram_init(void)
579{
580 struct mx6_ddr_sysinfo sysinfo = {
581
582 .dsize = 2,
583
584 .cs_density = 32,
585
586 .ncs = 1,
587 .cs1_mirror = 0,
588 .rtt_wr = 1 ,
589 .rtt_nom = 1 ,
590 .walat = 1,
591 .ralat = 5,
592 .mif3_mode = 3,
593 .bi_on = 1,
594 .sde_to_rst = 0x10,
595 .rst_to_cke = 0x23,
596 .ddr_type = DDR_TYPE_DDR3,
597 .refsel = 1,
598 .refr = 7,
599 };
600
601 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
602 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
603}
604
605void board_init_f(ulong dummy)
606{
607
608 arch_cpu_init();
609
610 ccgr_init();
611 gpr_init();
612
613
614 board_early_init_f();
615
616
617 timer_init();
618
619
620 preloader_console_init();
621
622
623 spl_dram_init();
624
625
626 memset(__bss_start, 0, __bss_end - __bss_start);
627
628
629 board_init_r(NULL, 0);
630}
631
632#endif
633
