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6#include <common.h>
7#include <i2c.h>
8#include <asm/io.h>
9#include <asm/arch/immap_ls102xa.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/fsl_serdes.h>
12#include <asm/arch/ls102xa_soc.h>
13#include <asm/arch/ls102xa_devdis.h>
14#include <hwconfig.h>
15#include <mmc.h>
16#include <fsl_csu.h>
17#include <fsl_esdhc.h>
18#include <fsl_ifc.h>
19#include <fsl_sec.h>
20#include <spl.h>
21#include <fsl_devdis.h>
22#include <fsl_validate.h>
23#include <fsl_ddr.h>
24#include "../common/sleep.h"
25#include "../common/qixis.h"
26#include "ls1021aqds_qixis.h"
27#ifdef CONFIG_U_QE
28#include <fsl_qe.h>
29#endif
30
31#define PIN_MUX_SEL_CAN 0x03
32#define PIN_MUX_SEL_IIC2 0xa0
33#define PIN_MUX_SEL_RGMII 0x00
34#define PIN_MUX_SEL_SAI 0x0c
35#define PIN_MUX_SEL_SDHC 0x00
36
37#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
38#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
39enum {
40 MUX_TYPE_CAN,
41 MUX_TYPE_IIC2,
42 MUX_TYPE_RGMII,
43 MUX_TYPE_SAI,
44 MUX_TYPE_SDHC,
45 MUX_TYPE_SD_PCI4,
46 MUX_TYPE_SD_PC_SA_SG_SG,
47 MUX_TYPE_SD_PC_SA_PC_SG,
48 MUX_TYPE_SD_PC_SG_SG,
49};
50
51enum {
52 GE0_CLK125,
53 GE2_CLK125,
54 GE1_CLK125,
55};
56
57int checkboard(void)
58{
59#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
60 char buf[64];
61#endif
62#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
63 u8 sw;
64#endif
65
66 puts("Board: LS1021AQDS\n");
67
68#ifdef CONFIG_SD_BOOT
69 puts("SD\n");
70#elif CONFIG_QSPI_BOOT
71 puts("QSPI\n");
72#else
73 sw = QIXIS_READ(brdcfg[0]);
74 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
75
76 if (sw < 0x8)
77 printf("vBank: %d\n", sw);
78 else if (sw == 0x8)
79 puts("PromJet\n");
80 else if (sw == 0x9)
81 puts("NAND\n");
82 else if (sw == 0x15)
83 printf("IFCCard\n");
84 else
85 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
86#endif
87
88#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
89 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
90 QIXIS_READ(id), QIXIS_READ(arch));
91
92 printf("FPGA: v%d (%s), build %d\n",
93 (int)QIXIS_READ(scver), qixis_read_tag(buf),
94 (int)qixis_read_minor());
95#endif
96
97 return 0;
98}
99
100unsigned long get_board_sys_clk(void)
101{
102 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
103
104 switch (sysclk_conf & 0x0f) {
105 case QIXIS_SYSCLK_64:
106 return 64000000;
107 case QIXIS_SYSCLK_83:
108 return 83333333;
109 case QIXIS_SYSCLK_100:
110 return 100000000;
111 case QIXIS_SYSCLK_125:
112 return 125000000;
113 case QIXIS_SYSCLK_133:
114 return 133333333;
115 case QIXIS_SYSCLK_150:
116 return 150000000;
117 case QIXIS_SYSCLK_160:
118 return 160000000;
119 case QIXIS_SYSCLK_166:
120 return 166666666;
121 }
122 return 66666666;
123}
124
125unsigned long get_board_ddr_clk(void)
126{
127 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
128
129 switch ((ddrclk_conf & 0x30) >> 4) {
130 case QIXIS_DDRCLK_100:
131 return 100000000;
132 case QIXIS_DDRCLK_125:
133 return 125000000;
134 case QIXIS_DDRCLK_133:
135 return 133333333;
136 }
137 return 66666666;
138}
139
140int select_i2c_ch_pca9547(u8 ch)
141{
142 int ret;
143
144 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
145 if (ret) {
146 puts("PCA: failed to select proper channel\n");
147 return ret;
148 }
149
150 return 0;
151}
152
153int dram_init(void)
154{
155
156
157
158
159
160 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
161 return fsl_initdram();
162}
163
164#ifdef CONFIG_FSL_ESDHC
165struct fsl_esdhc_cfg esdhc_cfg[1] = {
166 {CONFIG_SYS_FSL_ESDHC_ADDR},
167};
168
169int board_mmc_init(bd_t *bis)
170{
171 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
172
173 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
174}
175#endif
176
177int board_early_init_f(void)
178{
179 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
180
181#ifdef CONFIG_TSEC_ENET
182
183 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
184#endif
185
186#ifdef CONFIG_FSL_IFC
187 init_early_memctl_regs();
188#endif
189
190 arch_soc_init();
191
192#if defined(CONFIG_DEEP_SLEEP)
193 if (is_warm_boot())
194 fsl_dp_disable_console();
195#endif
196
197 return 0;
198}
199
200#ifdef CONFIG_SPL_BUILD
201void board_init_f(ulong dummy)
202{
203#ifdef CONFIG_NAND_BOOT
204 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
205 u32 porsr1, pinctl;
206
207
208
209
210
211
212 porsr1 = in_be32(&gur->porsr1);
213 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
214 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
215 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
216 pinctl);
217#endif
218
219
220 memset(__bss_start, 0, __bss_end - __bss_start);
221
222#ifdef CONFIG_FSL_IFC
223 init_early_memctl_regs();
224#endif
225
226 get_clocks();
227
228#if defined(CONFIG_DEEP_SLEEP)
229 if (is_warm_boot())
230 fsl_dp_disable_console();
231#endif
232
233 preloader_console_init();
234
235#ifdef CONFIG_SPL_I2C_SUPPORT
236 i2c_init_all();
237#endif
238
239 timer_init();
240 dram_init();
241
242
243#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
244 enable_layerscape_ns_access();
245#endif
246
247 board_init_r(NULL, 0);
248}
249#endif
250
251void config_etseccm_source(int etsec_gtx_125_mux)
252{
253 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
254
255 switch (etsec_gtx_125_mux) {
256 case GE0_CLK125:
257 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
258 debug("etseccm set to GE0_CLK125\n");
259 break;
260
261 case GE2_CLK125:
262 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
263 debug("etseccm set to GE2_CLK125\n");
264 break;
265
266 case GE1_CLK125:
267 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
268 debug("etseccm set to GE1_CLK125\n");
269 break;
270
271 default:
272 printf("Error! trying to set etseccm to invalid value\n");
273 break;
274 }
275}
276
277int config_board_mux(int ctrl_type)
278{
279 u8 reg12, reg14;
280
281 reg12 = QIXIS_READ(brdcfg[12]);
282 reg14 = QIXIS_READ(brdcfg[14]);
283
284 switch (ctrl_type) {
285 case MUX_TYPE_CAN:
286 config_etseccm_source(GE2_CLK125);
287 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
288 break;
289 case MUX_TYPE_IIC2:
290 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
291 break;
292 case MUX_TYPE_RGMII:
293 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
294 break;
295 case MUX_TYPE_SAI:
296 config_etseccm_source(GE2_CLK125);
297 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
298 break;
299 case MUX_TYPE_SDHC:
300 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
301 break;
302 case MUX_TYPE_SD_PCI4:
303 reg12 = 0x38;
304 break;
305 case MUX_TYPE_SD_PC_SA_SG_SG:
306 reg12 = 0x01;
307 break;
308 case MUX_TYPE_SD_PC_SA_PC_SG:
309 reg12 = 0x01;
310 break;
311 case MUX_TYPE_SD_PC_SG_SG:
312 reg12 = 0x21;
313 break;
314 default:
315 printf("Wrong mux interface type\n");
316 return -1;
317 }
318
319 QIXIS_WRITE(brdcfg[12], reg12);
320 QIXIS_WRITE(brdcfg[14], reg14);
321
322 return 0;
323}
324
325int config_serdes_mux(void)
326{
327 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
328 u32 cfg;
329
330 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
331 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
332
333 switch (cfg) {
334 case 0x0:
335 config_board_mux(MUX_TYPE_SD_PCI4);
336 break;
337 case 0x30:
338 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
339 break;
340 case 0x60:
341 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
342 break;
343 case 0x70:
344 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
345 break;
346 default:
347 printf("SRDS1 prtcl:0x%x\n", cfg);
348 break;
349 }
350
351 return 0;
352}
353
354#ifdef CONFIG_BOARD_LATE_INIT
355int board_late_init(void)
356{
357#ifdef CONFIG_CHAIN_OF_TRUST
358 fsl_setenv_chain_of_trust();
359#endif
360
361 return 0;
362}
363#endif
364
365int misc_init_r(void)
366{
367 int conflict_flag;
368
369
370 conflict_flag = 0;
371 if (hwconfig("sdhc"))
372 conflict_flag++;
373 if (hwconfig("iic2"))
374 conflict_flag++;
375 if (conflict_flag > 1) {
376 printf("WARNING: pin conflict !\n");
377 return 0;
378 }
379
380 conflict_flag = 0;
381 if (hwconfig("rgmii"))
382 conflict_flag++;
383 if (hwconfig("can"))
384 conflict_flag++;
385 if (hwconfig("sai"))
386 conflict_flag++;
387 if (conflict_flag > 1) {
388 printf("WARNING: pin conflict !\n");
389 return 0;
390 }
391
392 if (hwconfig("can"))
393 config_board_mux(MUX_TYPE_CAN);
394 else if (hwconfig("rgmii"))
395 config_board_mux(MUX_TYPE_RGMII);
396 else if (hwconfig("sai"))
397 config_board_mux(MUX_TYPE_SAI);
398
399 if (hwconfig("iic2"))
400 config_board_mux(MUX_TYPE_IIC2);
401 else if (hwconfig("sdhc"))
402 config_board_mux(MUX_TYPE_SDHC);
403
404#ifdef CONFIG_FSL_DEVICE_DISABLE
405 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
406#endif
407#ifdef CONFIG_FSL_CAAM
408 return sec_init();
409#endif
410 return 0;
411}
412
413int board_init(void)
414{
415#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
416 erratum_a010315();
417#endif
418#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
419 erratum_a009942_check_cpo();
420#endif
421
422 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
423
424#ifndef CONFIG_SYS_FSL_NO_SERDES
425 fsl_serdes_init();
426 config_serdes_mux();
427#endif
428
429 ls102xa_smmu_stream_id_init();
430
431#ifdef CONFIG_U_QE
432 u_qe_init();
433#endif
434
435 return 0;
436}
437
438#if defined(CONFIG_DEEP_SLEEP)
439void board_sleep_prepare(void)
440{
441#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
442 enable_layerscape_ns_access();
443#endif
444}
445#endif
446
447int ft_board_setup(void *blob, bd_t *bd)
448{
449 ft_cpu_setup(blob, bd);
450
451#ifdef CONFIG_PCI
452 ft_pci_setup(blob, bd);
453#endif
454
455 return 0;
456}
457
458u8 flash_read8(void *addr)
459{
460 return __raw_readb(addr + 1);
461}
462
463void flash_write16(u16 val, void *addr)
464{
465 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
466
467 __raw_writew(shftval, addr);
468}
469
470u16 flash_read16(void *addr)
471{
472 u16 val = __raw_readw(addr);
473
474 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
475}
476
