LXR uboot/board/freescale/mpc8313erdb/sdram.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
   4 *
   5 * Authors: Nick.Spence@freescale.com
   6 *          Wilson.Lo@freescale.com
   7 *          scottwood@freescale.com
   8 */
   9
  10#include <common.h>
  11#include <mpc83xx.h>
  12#include <spd_sdram.h>
  13
  14#include <asm/bitops.h>
  15#include <asm/io.h>
  16
  17#include <asm/processor.h>
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  22static void resume_from_sleep(void)
  23{
  24        u32 magic = *(u32 *)0;
  25
  26        typedef void (*func_t)(void);
  27        func_t resume = *(func_t *)4;
  28
  29        if (magic == 0xf5153ae5)
  30                resume();
  31
  32        gd->flags &= ~GD_FLG_SILENT;
  33        puts("\nResume from sleep failed: bad magic word\n");
  34}
  35#endif
  36
  37/* Fixed sdram init -- doesn't use serial presence detect.
  38 *
  39 * This is useful for faster booting in configs where the RAM is unlikely
  40 * to be changed, or for things like NAND booting where space is tight.
  41 */
  42static long fixed_sdram(void)
  43{
  44        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  45
  46#ifndef CONFIG_SYS_RAMBOOT
  47        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  48        u32 msize_log2 = __ilog2(msize);
  49
  50        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  51        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  52        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  53
  54        /*
  55         * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  56         * or the DDR2 controller may fail to initialize correctly.
  57         */
  58        __udelay(50000);
  59
  60#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  61#warning Chip select bounds is only configurable in 16MB increments
  62#endif
  63        im->ddr.csbnds[0].csbnds =
  64                ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  65                (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
  66                        CSBNDS_EA);
  67        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  68
  69        /* Currently we use only one CS, so disable the other bank. */
  70        im->ddr.cs_config[1] = 0;
  71
  72        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
  73        im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  74        im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  75        im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  76        im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  77
  78#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  79        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  80                im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
  81        else
  82#endif
  83                im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
  84
  85        im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
  86        im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  87        im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
  88
  89        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  90        sync();
  91
  92        /* enable DDR controller */
  93        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  94#endif
  95
  96        return msize;
  97}
  98
  99int dram_init(void)
 100{
 101        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 102        volatile fsl_lbc_t *lbc = &im->im_lbc;
 103        u32 msize;
 104
 105        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 106                return -ENXIO;
 107
 108        /* DDR SDRAM - Main SODIMM */
 109        msize = fixed_sdram();
 110
 111        /* Local Bus setup lbcr and mrtpr */
 112        lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
 113        /* LB refresh timer prescal, 266MHz/32 */
 114        lbc->mrtpr = 0x20000000;
 115        sync();
 116
 117#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
 118        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 119                resume_from_sleep();
 120#endif
 121
 122        /* return total bus SDRAM size(bytes)  -- DDR */
 123        gd->ram_size = msize;
 124
 125        return 0;
 126}
 127