LXR uboot/board/freescale/mpc832xemds/mpc832xemds.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4 *
   5 * Dave Liu <daveliu@freescale.com>
   6 */
   7
   8#include <common.h>
   9#include <ioports.h>
  10#include <mpc83xx.h>
  11#include <i2c.h>
  12#include <miiphy.h>
  13#include <command.h>
  14#if defined(CONFIG_PCI)
  15#include <pci.h>
  16#endif
  17#include <asm/mmu.h>
  18#if defined(CONFIG_OF_LIBFDT)
  19#include <linux/libfdt.h>
  20#endif
  21#if defined(CONFIG_PQ_MDS_PIB)
  22#include "../common/pq-mds-pib.h"
  23#endif
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27const qe_iop_conf_t qe_iop_conf_tab[] = {
  28        /* ETH3 */
  29        {1,  0, 1, 0, 1}, /* TxD0 */
  30        {1,  1, 1, 0, 1}, /* TxD1 */
  31        {1,  2, 1, 0, 1}, /* TxD2 */
  32        {1,  3, 1, 0, 1}, /* TxD3 */
  33        {1,  9, 1, 0, 1}, /* TxER */
  34        {1, 12, 1, 0, 1}, /* TxEN */
  35        {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
  36
  37        {1,  4, 2, 0, 1}, /* RxD0 */
  38        {1,  5, 2, 0, 1}, /* RxD1 */
  39        {1,  6, 2, 0, 1}, /* RxD2 */
  40        {1,  7, 2, 0, 1}, /* RxD3 */
  41        {1,  8, 2, 0, 1}, /* RxER */
  42        {1, 10, 2, 0, 1}, /* RxDV */
  43        {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
  44        {1, 11, 2, 0, 1}, /* COL */
  45        {1, 13, 2, 0, 1}, /* CRS */
  46
  47        /* ETH4 */
  48        {1, 18, 1, 0, 1}, /* TxD0 */
  49        {1, 19, 1, 0, 1}, /* TxD1 */
  50        {1, 20, 1, 0, 1}, /* TxD2 */
  51        {1, 21, 1, 0, 1}, /* TxD3 */
  52        {1, 27, 1, 0, 1}, /* TxER */
  53        {1, 30, 1, 0, 1}, /* TxEN */
  54        {3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
  55
  56        {1, 22, 2, 0, 1}, /* RxD0 */
  57        {1, 23, 2, 0, 1}, /* RxD1 */
  58        {1, 24, 2, 0, 1}, /* RxD2 */
  59        {1, 25, 2, 0, 1}, /* RxD3 */
  60        {1, 26, 1, 0, 1}, /* RxER */
  61        {1, 28, 2, 0, 1}, /* Rx_DV */
  62        {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
  63        {1, 29, 2, 0, 1}, /* COL */
  64        {1, 31, 2, 0, 1}, /* CRS */
  65
  66        {3,  4, 3, 0, 2}, /* MDIO */
  67        {3,  5, 1, 0, 2}, /* MDC */
  68
  69        {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  70};
  71
  72int board_early_init_f(void)
  73{
  74        volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
  75
  76        /* Enable flash write */
  77        bcsr[9] &= ~0x08;
  78
  79        return 0;
  80}
  81
  82int board_early_init_r(void)
  83{
  84#ifdef CONFIG_PQ_MDS_PIB
  85        pib_init();
  86#endif
  87        return 0;
  88}
  89
  90int fixed_sdram(void);
  91
  92int dram_init(void)
  93{
  94        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  95        u32 msize = 0;
  96
  97        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  98                return -ENXIO;
  99
 100        /* DDR SDRAM - Main SODIMM */
 101        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 102
 103        msize = fixed_sdram();
 104
 105        /* set total bus SDRAM size(bytes)  -- DDR */
 106        gd->ram_size = msize * 1024 * 1024;
 107
 108        return 0;
 109}
 110
 111/*************************************************************************
 112 *  fixed sdram init -- doesn't use serial presence detect.
 113 ************************************************************************/
 114int fixed_sdram(void)
 115{
 116        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 117        u32 msize = 0;
 118        u32 ddr_size;
 119        u32 ddr_size_log2;
 120
 121        msize = CONFIG_SYS_DDR_SIZE;
 122        for (ddr_size = msize << 20, ddr_size_log2 = 0;
 123             (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 124                if (ddr_size & 1) {
 125                        return -1;
 126                }
 127        }
 128        im->sysconf.ddrlaw[0].ar =
 129            LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 130#if (CONFIG_SYS_DDR_SIZE != 128)
 131#warning Currenly any ddr size other than 128 is not supported
 132#endif
 133        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 134        im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 135        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 136        im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 137        im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 138        im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 139        im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 140        im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 141        im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 142        im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 143        im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 144        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 145        __asm__ __volatile__ ("sync");
 146        udelay(200);
 147
 148        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 149        __asm__ __volatile__ ("sync");
 150        return msize;
 151}
 152
 153int checkboard(void)
 154{
 155        puts("Board: Freescale MPC832XEMDS\n");
 156        return 0;
 157}
 158
 159#if defined(CONFIG_OF_BOARD_SETUP)
 160int ft_board_setup(void *blob, bd_t *bd)
 161{
 162        ft_cpu_setup(blob, bd);
 163#ifdef CONFIG_PCI
 164        ft_pci_setup(blob, bd);
 165#endif
 166
 167        return 0;
 168}
 169#endif
 170