1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. 4 * Dave Liu <daveliu@freescale.com> 5 */ 6 7#ifndef __FSL_SATA_H__ 8#define __FSL_SATA_H__ 9 10#define SATA_HC_MAX_NUM 4 /* Max host controller numbers */ 11#define SATA_HC_MAX_CMD 16 /* Max command queue depth per host controller */ 12#define SATA_HC_MAX_PORT 16 /* Max port number per host controller */ 13 14/* 15* SATA Host Controller Registers 16*/ 17typedef struct fsl_sata_reg { 18 /* SATA command registers */ 19 u32 cqr; /* Command queue register */ 20 u8 res1[0x4]; 21 u32 car; /* Command active register */ 22 u8 res2[0x4]; 23 u32 ccr; /* Command completed register */ 24 u8 res3[0x4]; 25 u32 cer; /* Command error register */ 26 u8 res4[0x4]; 27 u32 der; /* Device error register */ 28 u32 chba; /* Command header base address */ 29 u32 hstatus; /* Host status register */ 30 u32 hcontrol; /* Host control register */ 31 u32 cqpmp; /* Port number queue register */ 32 u32 sig; /* Signature register */ 33 u32 icc; /* Interrupt coalescing control register */ 34 u8 res5[0xc4]; 35 36 /* SATA supperset registers */ 37 u32 sstatus; /* SATA interface status register */ 38 u32 serror; /* SATA interface error register */ 39 u32 scontrol; /* SATA interface control register */ 40 u32 snotification; /* SATA interface notification register */ 41 u8 res6[0x30]; 42 43 /* SATA control status registers */ 44 u32 transcfg; /* Transport layer configuration */ 45 u32 transstatus; /* Transport layer status */ 46 u32 linkcfg; /* Link layer configuration */ 47 u32 linkcfg1; /* Link layer configuration1 */ 48 u32 linkcfg2; /* Link layer configuration2 */ 49 u32 linkstatus; /* Link layer status */ 50 u32 linkstatus1; /* Link layer status1 */ 51 u32 phyctrlcfg; /* PHY control configuration */ 52 u8 res7[0x2b0]; 53 54 /* SATA system control registers */ 55 u32 syspr; /* System priority register - big endian */ 56 u8 res8[0xbec]; 57} __attribute__ ((packed)) fsl_sata_reg_t; 58 59/* HStatus register 60*/ 61#define HSTATUS_ONOFF 0x80000000 /* Online/offline status */ 62#define HSTATUS_FORCE_OFFLINE 0x40000000 /* In process going offline */ 63#define HSTATUS_BIST_ERR 0x20000000 64 65/* Fatal error */ 66#define HSTATUS_MASTER_ERR 0x00004000 67#define HSTATUS_DATA_UNDERRUN 0x00002000 68#define HSTATUS_DATA_OVERRUN 0x00001000 69#define HSTATUS_CRC_ERR_TX 0x00000800 70#define HSTATUS_CRC_ERR_RX 0x00000400 71#define HSTATUS_FIFO_OVERFLOW_TX 0x00000200 72#define HSTATUS_FIFO_OVERFLOW_RX 0x00000100 73#define HSTATUS_FATAL_ERR_ALL (HSTATUS_MASTER_ERR | \ 74 HSTATUS_DATA_UNDERRUN | \ 75 HSTATUS_DATA_OVERRUN | \ 76 HSTATUS_CRC_ERR_TX | \ 77 HSTATUS_CRC_ERR_RX | \ 78 HSTATUS_FIFO_OVERFLOW_TX | \ 79 HSTATUS_FIFO_OVERFLOW_RX) 80/* Interrupt status */ 81#define HSTATUS_FATAL_ERR 0x00000020 82#define HSTATUS_PHY_RDY 0x00000010 83#define HSTATUS_SIGNATURE 0x00000008 84#define HSTATUS_SNOTIFY 0x00000004 85#define HSTATUS_DEVICE_ERR 0x00000002 86#define HSTATUS_CMD_COMPLETE 0x00000001 87 88/* HControl register 89*/ 90#define HCONTROL_ONOFF 0x80000000 /* Online or offline request */ 91#define HCONTROL_FORCE_OFFLINE 0x40000000 /* Force offline request */ 92#define HCONTROL_ENTERPRISE_EN 0x10000000 /* Enterprise mode enabled */ 93#define HCONTROL_HDR_SNOOP 0x00000400 /* Command header snoop */ 94#define HCONTROL_PMP_ATTACHED 0x00000200 /* Port multiplier attached */ 95 96/* Interrupt enable */ 97#define HCONTROL_FATAL_ERR 0x00000020 98#define HCONTROL_PHY_RDY 0x00000010 99#define HCONTROL_SIGNATURE 0x00000008 100#define HCONTROL_SNOTIFY 0x00000004 101#define HCONTROL_DEVICE_ERR 0x00000002 102#define HCONTROL_CMD_COMPLETE 0x00000001 103 104#define HCONTROL_INT_EN_ALL (HCONTROL_FATAL_ERR | \ 105 HCONTROL_PHY_RDY | \ 106 HCONTROL_SIGNATURE | \ 107 HCONTROL_SNOTIFY | \ 108 HCONTROL_DEVICE_ERR | \ 109 HCONTROL_CMD_COMPLETE) 110 111/* SStatus register 112*/ 113#define SSTATUS_IPM_MASK 0x00000780 114#define SSTATUS_IPM_NOPRESENT 0x00000000 115#define SSTATUS_IPM_ACTIVE 0x00000080 116#define SSTATUS_IPM_PATIAL 0x00000100 117#define SSTATUS_IPM_SLUMBER 0x00000300 118 119#define SSTATUS_SPD_MASK 0x000000f0 120#define SSTATUS_SPD_GEN1 0x00000010 121#define SSTATUS_SPD_GEN2 0x00000020 122 123#define SSTATUS_DET_MASK 0x0000000f 124#define SSTATUS_DET_NODEVICE 0x00000000 125#define SSTATUS_DET_DISCONNECT 0x00000001 126#define SSTATUS_DET_CONNECT 0x00000003 127#define SSTATUS_DET_PHY_OFFLINE 0x00000004 128 129/* SControl register 130*/ 131#define SCONTROL_SPM_MASK 0x0000f000 132#define SCONTROL_SPM_GO_PARTIAL 0x00001000 133#define SCONTROL_SPM_GO_SLUMBER 0x00002000 134#define SCONTROL_SPM_GO_ACTIVE 0x00004000 135 136#define SCONTROL_IPM_MASK 0x00000f00 137#define SCONTROL_IPM_NO_RESTRICT 0x00000000 138#define SCONTROL_IPM_PARTIAL 0x00000100 139#define SCONTROL_IPM_SLUMBER 0x00000200 140#define SCONTROL_IPM_PART_SLUM 0x00000300 141 142#define SCONTROL_SPD_MASK 0x000000f0 143#define SCONTROL_SPD_NO_RESTRICT 0x00000000 144#define SCONTROL_SPD_GEN1 0x00000010 145#define SCONTROL_SPD_GEN2 0x00000020 146 147#define SCONTROL_DET_MASK 0x0000000f 148#define SCONTROL_DET_HRESET 0x00000001 149#define SCONTROL_DET_DISABLE 0x00000004 150 151/* TransCfg register 152*/ 153#define TRANSCFG_DFIS_SIZE_SHIFT 16 154#define TRANSCFG_RX_WATER_MARK_MASK 0x0000001f 155 156/* PhyCtrlCfg register 157*/ 158#define PHYCTRLCFG_FPRFTI_MASK 0x00000018 159#define PHYCTRLCFG_LOOPBACK_MASK 0x0000000e 160 161/* 162* Command Header Entry 163*/ 164typedef struct cmd_hdr_entry { 165 __le32 cda; /* Command Descriptor Address, 166 4 bytes aligned */ 167 __le32 prde_fis_len; /* Number of PRD entries and FIS length */ 168 __le32 ttl; /* Total transfer length */ 169 __le32 attribute; /* the attribute of command */ 170} __attribute__ ((packed)) cmd_hdr_entry_t; 171 172#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry) 173 174/* cda 175*/ 176#define CMD_HDR_CDA_ALIGN 4 177 178/* prde_fis_len 179*/ 180#define CMD_HDR_PRD_ENTRY_SHIFT 16 181#define CMD_HDR_PRD_ENTRY_MASK 0x003f0000 182#define CMD_HDR_FIS_LEN_SHIFT 2 183 184/* attribute 185*/ 186#define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */ 187#define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */ 188#define CMD_HDR_ATTR_SNOOP 0x00000200 /* Snoop enable for all descriptor */ 189#define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */ 190#define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */ 191#define CMD_HDR_ATTR_BIST 0x00000040 /* BIST - require the host to enter BIST mode */ 192#define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */ 193#define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */ 194 195/* command type 196*/ 197enum cmd_type { 198 CMD_VENDOR_BIST, 199 CMD_BIST, 200 CMD_RESET, /* SRST or device reset */ 201 CMD_ATAPI, 202 CMD_NCQ, 203 CMD_ATA, /* None of all above */ 204}; 205 206/* 207* Command Header Table 208*/ 209typedef struct cmd_hdr_tbl { 210 cmd_hdr_entry_t cmd_slot[SATA_HC_MAX_CMD]; 211} __attribute__ ((packed)) cmd_hdr_tbl_t; 212 213#define SATA_HC_CMD_HDR_TBL_SIZE sizeof(struct cmd_hdr_tbl) 214#define SATA_HC_CMD_HDR_TBL_ALIGN 4 215 216/* 217* PRD entry - Physical Region Descriptor entry 218*/ 219typedef struct prd_entry { 220 __le32 dba; /* Data base address, 4 bytes aligned */ 221 u32 res1; 222 u32 res2; 223 __le32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */ 224} __attribute__ ((packed)) prd_entry_t; 225 226#define SATA_HC_CMD_DESC_PRD_SIZE sizeof(struct prd_entry) 227 228/* dba 229*/ 230#define PRD_ENTRY_DBA_ALIGN 4 231 232/* ext_c_ddc 233*/ 234#define PRD_ENTRY_EXT 0x80000000 /* extension flag */ 235#ifdef CONFIG_FSL_SATA_V2 236#define PRD_ENTRY_DATA_SNOOP 0x10000000 /* Data snoop enable */ 237#else 238#define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Data snoop enable */ 239#endif 240#define PRD_ENTRY_LEN_MASK 0x003fffff /* Data word count */ 241 242#define PRD_ENTRY_MAX_XFER_SZ (PRD_ENTRY_LEN_MASK + 1) 243 244/* 245 * This SATA host controller supports a max of 16 direct PRD entries, but if use 246 * chained indirect PRD entries, then the contollers supports upto a max of 63 247 * entries including direct and indirect PRD entries. 248 * The PRDT is an array of 63 PRD entries contigiously, but the PRD entries#15 249 * will be setup as an indirect descriptor, pointing to it's next (contigious) 250 * PRD entries#16. 251 */ 252#define SATA_HC_MAX_PRD 63 /* Max PRD entry numbers per command */ 253#define SATA_HC_MAX_PRD_DIRECT 16 /* Direct PRDT entries */ 254#define SATA_HC_MAX_PRD_USABLE (SATA_HC_MAX_PRD - 1) 255#define SATA_HC_MAX_XFER_LEN 0x4000000 256 257/* 258* PRDT - Physical Region Descriptor Table 259*/ 260typedef struct prdt { 261 prd_entry_t prdt[SATA_HC_MAX_PRD]; 262} __attribute__ ((packed)) prdt_t; 263 264/* 265* Command Descriptor 266*/ 267#define SATA_HC_CMD_DESC_CFIS_SIZE 32 /* bytes */ 268#define SATA_HC_CMD_DESC_SFIS_SIZE 32 /* bytes */ 269#define SATA_HC_CMD_DESC_ACMD_SIZE 16 /* bytes */ 270#define SATA_HC_CMD_DESC_RES 16 /* bytes */ 271 272typedef struct cmd_desc { 273 u8 cfis[SATA_HC_CMD_DESC_CFIS_SIZE]; 274 u8 sfis[SATA_HC_CMD_DESC_SFIS_SIZE]; 275 u8 acmd[SATA_HC_CMD_DESC_ACMD_SIZE]; 276 u8 res[SATA_HC_CMD_DESC_RES]; 277 prd_entry_t prdt[SATA_HC_MAX_PRD]; 278} __attribute__ ((packed)) cmd_desc_t; 279 280#define SATA_HC_CMD_DESC_SIZE sizeof(struct cmd_desc) 281#define SATA_HC_CMD_DESC_ALIGN 4 282 283/* 284 * SATA device driver info 285 */ 286typedef struct fsl_sata_info { 287 u32 sata_reg_base; 288 u32 flags; 289} fsl_sata_info_t; 290 291#define FLAGS_DMA 0x00000000 292#define FLAGS_FPDMA 0x00000001 293 294/* 295 * SATA device driver struct 296 */ 297typedef struct fsl_sata { 298 char name[12]; 299 fsl_sata_reg_t *reg_base; /* the base address of controller register */ 300 void *cmd_hdr_tbl_offset; /* alloc address of command header table */ 301 cmd_hdr_tbl_t *cmd_hdr; /* aligned address of command header table */ 302 void *cmd_desc_offset; /* alloc address of command descriptor */ 303 cmd_desc_t *cmd_desc; /* aligned address of command descriptor */ 304 int link; /* PHY link status */ 305 /* device attribute */ 306 int ata_device_type; /* device type */ 307 int lba48; 308 int queue_depth; /* Max NCQ queue depth */ 309 u16 pio; 310 u16 mwdma; 311 u16 udma; 312 int wcache; 313 int flush; 314 int flush_ext; 315 u32 dma_flag; 316} fsl_sata_t; 317 318#define READ_CMD 0 319#define WRITE_CMD 1 320 321#endif /* __FSL_SATA_H__ */ 322