LXR uboot/drivers/ddr/fsl/ddr4_dimm

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2014-2016 Freescale Semiconductor, Inc.
   4 * Copyright 2017-2018 NXP Semiconductor
   5 *
   6 * calculate the organization and timing parameter
   7 * from ddr3 spd, please refer to the spec
   8 * JEDEC standard No.21-C 4_01_02_12R23A.pdf
   9 *
  10 *
  11 */
  12
  13#include <common.h>
  14#include <fsl_ddr_sdram.h>
  15
  16#include <fsl_ddr.h>
  17
  18/*
  19 * Calculate the Density of each Physical Rank.
  20 * Returned size is in bytes.
  21 *
  22 * Total DIMM size =
  23 * sdram capacity(bit) / 8 * primary bus width / sdram width
  24 *                     * Logical Ranks per DIMM
  25 *
  26 * where: sdram capacity  = spd byte4[3:0]
  27 *        primary bus width = spd byte13[2:0]
  28 *        sdram width = spd byte12[2:0]
  29 *        Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
  30 *                                 spd byte12{5:3] * spd byte6[6:4] for 3DS
  31 *
  32 * To simplify each rank size = total DIMM size / Number of Package Ranks
  33 * where Number of Package Ranks = spd byte12[5:3]
  34 *
  35 * SPD byte4 - sdram density and banks
  36 *      bit[3:0]        size(bit)       size(byte)
  37 *      0000            256Mb           32MB
  38 *      0001            512Mb           64MB
  39 *      0010            1Gb             128MB
  40 *      0011            2Gb             256MB
  41 *      0100            4Gb             512MB
  42 *      0101            8Gb             1GB
  43 *      0110            16Gb            2GB
  44 *      0111            32Gb            4GB
  45 *
  46 * SPD byte13 - module memory bus width
  47 *      bit[2:0]        primary bus width
  48 *      000             8bits
  49 *      001             16bits
  50 *      010             32bits
  51 *      011             64bits
  52 *
  53 * SPD byte12 - module organization
  54 *      bit[2:0]        sdram device width
  55 *      000             4bits
  56 *      001             8bits
  57 *      010             16bits
  58 *      011             32bits
  59 *
  60 * SPD byte12 - module organization
  61 *      bit[5:3]        number of package ranks per DIMM
  62 *      000             1
  63 *      001             2
  64 *      010             3
  65 *      011             4
  66 *
  67 * SPD byte6 - SDRAM package type
  68 *      bit[6:4]        Die count
  69 *      000             1
  70 *      001             2
  71 *      010             3
  72 *      011             4
  73 *      100             5
  74 *      101             6
  75 *      110             7
  76 *      111             8
  77 *
  78 * SPD byte6 - SRAM package type
  79 *      bit[1:0]        Signal loading
  80 *      00              Not specified
  81 *      01              Multi load stack
  82 *      10              Sigle load stack (3DS)
  83 *      11              Reserved
  84 */
  85static unsigned long long
  86compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
  87{
  88        unsigned long long bsize;
  89
  90        int nbit_sdram_cap_bsize = 0;
  91        int nbit_primary_bus_width = 0;
  92        int nbit_sdram_width = 0;
  93        int die_count = 0;
  94        bool package_3ds;
  95
  96        if ((spd->density_banks & 0xf) <= 7)
  97                nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
  98        if ((spd->bus_width & 0x7) < 4)
  99                nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
 100        if ((spd->organization & 0x7) < 4)
 101                nbit_sdram_width = (spd->organization & 0x7) + 2;
 102        package_3ds = (spd->package_type & 0x3) == 0x2;
 103        if ((spd->package_type & 0x80) && !package_3ds) { /* other than 3DS */
 104                printf("Warning: not supported SDRAM package type\n");
 105                return 0;
 106        }
 107        if (package_3ds)
 108                die_count = (spd->package_type >> 4) & 0x7;
 109
 110        bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
 111                         nbit_primary_bus_width - nbit_sdram_width +
 112                         die_count);
 113
 114        debug("DDR: DDR rank density = 0x%16llx\n", bsize);
 115
 116        return bsize;
 117}
 118
 119#define spd_to_ps(mtb, ftb)     \
 120        (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
 121/*
 122 * ddr_compute_dimm_parameters for DDR4 SPD
 123 *
 124 * Compute DIMM parameters based upon the SPD information in spd.
 125 * Writes the results to the dimm_params_t structure pointed by pdimm.
 126 *
 127 */
 128unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
 129                                         const generic_spd_eeprom_t *spd,
 130                                         dimm_params_t *pdimm,
 131                                         unsigned int dimm_number)
 132{
 133        unsigned int retval;
 134        int i;
 135        const u8 udimm_rc_e_dq[18] = {
 136                0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
 137                0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
 138        };
 139        int spd_error = 0;
 140        u8 *ptr;
 141        u8 val;
 142
 143        if (spd->mem_type) {
 144                if (spd->mem_type != SPD_MEMTYPE_DDR4) {
 145                        printf("Ctrl %u DIMM %u: is not a DDR4 SPD.\n",
 146                               ctrl_num, dimm_number);
 147                        return 1;
 148                }
 149        } else {
 150                memset(pdimm, 0, sizeof(dimm_params_t));
 151                return 1;
 152        }
 153
 154        retval = ddr4_spd_check(spd);
 155        if (retval) {
 156                printf("DIMM %u: failed checksum\n", dimm_number);
 157                return 2;
 158        }
 159
 160        /*
 161         * The part name in ASCII in the SPD EEPROM is not null terminated.
 162         * Guarantee null termination here by presetting all bytes to 0
 163         * and copying the part name in ASCII from the SPD onto it
 164         */
 165        memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 166        if ((spd->info_size_crc & 0xF) > 2)
 167                memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
 168
 169        /* DIMM organization parameters */
 170        pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
 171        pdimm->rank_density = compute_ranksize(spd);
 172        pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
 173        pdimm->die_density = spd->density_banks & 0xf;
 174        pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
 175        if ((spd->bus_width >> 3) & 0x3)
 176                pdimm->ec_sdram_width = 8;
 177        else
 178                pdimm->ec_sdram_width = 0;
 179        pdimm->data_width = pdimm->primary_sdram_width
 180                          + pdimm->ec_sdram_width;
 181        pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
 182        pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ?
 183                             (spd->package_type >> 4) & 0x7 : 0;
 184
 185        /* These are the types defined by the JEDEC SPD spec */
 186        pdimm->mirrored_dimm = 0;
 187        pdimm->registered_dimm = 0;
 188        switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
 189        case DDR4_SPD_MODULETYPE_RDIMM:
 190                /* Registered/buffered DIMMs */
 191                pdimm->registered_dimm = 1;
 192                if (spd->mod_section.registered.reg_map & 0x1)
 193                        pdimm->mirrored_dimm = 1;
 194                val = spd->mod_section.registered.ca_stren;
 195                pdimm->rcw[3] = val >> 4;
 196                pdimm->rcw[4] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
 197                val = spd->mod_section.registered.clk_stren;
 198                pdimm->rcw[5] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
 199                /* Not all in SPD. For convience only. Boards may overwrite. */
 200                pdimm->rcw[6] = 0xf;
 201                /*
 202                 * A17 only used for 16Gb and above devices.
 203                 * C[2:0] only used for 3DS.
 204                 */
 205                pdimm->rcw[8] = pdimm->die_density >= 0x6 ? 0x0 : 0x8 |
 206                                (pdimm->package_3ds > 0x3 ? 0x0 :
 207                                 (pdimm->package_3ds > 0x1 ? 0x1 :
 208                                  (pdimm->package_3ds > 0 ? 0x2 : 0x3)));
 209                if (pdimm->package_3ds || pdimm->n_ranks != 4)
 210                        pdimm->rcw[13] = 0xc;
 211                else
 212                        pdimm->rcw[13] = 0xd;   /* Fix encoded by board */
 213
 214                break;
 215
 216        case DDR4_SPD_MODULETYPE_UDIMM:
 217        case DDR4_SPD_MODULETYPE_SO_DIMM:
 218                /* Unbuffered DIMMs */
 219                if (spd->mod_section.unbuffered.addr_mapping & 0x1)
 220                        pdimm->mirrored_dimm = 1;
 221                if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
 222                    (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
 223                        /* Fix SPD error found on DIMMs with raw card E0 */
 224                        for (i = 0; i < 18; i++) {
 225                                if (spd->mapping[i] == udimm_rc_e_dq[i])
 226                                        continue;
 227                                spd_error = 1;
 228                                debug("SPD byte %d: 0x%x, should be 0x%x\n",
 229                                      60 + i, spd->mapping[i],
 230                                      udimm_rc_e_dq[i]);
 231                                ptr = (u8 *)&spd->mapping[i];
 232                                *ptr = udimm_rc_e_dq[i];
 233                        }
 234                        if (spd_error)
 235                                puts("SPD DQ mapping error fixed\n");
 236                }
 237                break;
 238
 239        default:
 240                printf("unknown module_type 0x%02X\n", spd->module_type);
 241                return 1;
 242        }
 243
 244        /* SDRAM device parameters */
 245        pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
 246        pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
 247        pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
 248        pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
 249
 250        /*
 251         * The SPD spec has not the ECC bit,
 252         * We consider the DIMM as ECC capability
 253         * when the extension bus exist
 254         */
 255        if (pdimm->ec_sdram_width)
 256                pdimm->edc_config = 0x02;
 257        else
 258                pdimm->edc_config = 0x00;
 259
 260        /*
 261         * The SPD spec has not the burst length byte
 262         * but DDR4 spec has nature BL8 and BC4,
 263         * BL8 -bit3, BC4 -bit2
 264         */
 265        pdimm->burst_lengths_bitmask = 0x0c;
 266
 267        /* MTB - medium timebase
 268         * The MTB in the SPD spec is 125ps,
 269         *
 270         * FTB - fine timebase
 271         * use 1/10th of ps as our unit to avoid floating point
 272         * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
 273         */
 274        if ((spd->timebases & 0xf) == 0x0) {
 275                pdimm->mtb_ps = 125;
 276                pdimm->ftb_10th_ps = 10;
 277
 278        } else {
 279                printf("Unknown Timebases\n");
 280        }
 281
 282        /* sdram minimum cycle time */
 283        pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
 284
 285        /* sdram max cycle time */
 286        pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
 287
 288        /*
 289         * CAS latency supported
 290         * bit0 - CL7
 291         * bit4 - CL11
 292         * bit8 - CL15
 293         * bit12- CL19
 294         * bit16- CL23
 295         */
 296        pdimm->caslat_x  = (spd->caslat_b1 << 7)        |
 297                           (spd->caslat_b2 << 15)       |
 298                           (spd->caslat_b3 << 23);
 299
 300        BUG_ON(spd->caslat_b4 != 0);
 301
 302        /*
 303         * min CAS latency time
 304         */
 305        pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
 306
 307        /*
 308         * min RAS to CAS delay time
 309         */
 310        pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
 311
 312        /*
 313         * Min Row Precharge Delay Time
 314         */
 315        pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
 316
 317        /* min active to precharge delay time */
 318        pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
 319                          spd->tras_min_lsb) * pdimm->mtb_ps;
 320
 321        /* min active to actice/refresh delay time */
 322        pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
 323                                   spd->trc_min_lsb), spd->fine_trc_min);
 324        /* Min Refresh Recovery Delay Time */
 325        pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
 326                       pdimm->mtb_ps;
 327        pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
 328                       pdimm->mtb_ps;
 329        pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
 330                        pdimm->mtb_ps;
 331        /* min four active window delay time */
 332        pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
 333                        pdimm->mtb_ps;
 334
 335        /* min row active to row active delay time, different bank group */
 336        pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
 337        /* min row active to row active delay time, same bank group */
 338        pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
 339        /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
 340        pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
 341
 342        if (pdimm->package_3ds) {
 343                if (pdimm->die_density <= 0x4) {
 344                        pdimm->trfc_slr_ps = 260000;
 345                } else if (pdimm->die_density <= 0x5) {
 346                        pdimm->trfc_slr_ps = 350000;
 347                } else {
 348                        printf("WARN: Unsupported logical rank density 0x%x\n",
 349                               pdimm->die_density);
 350                }
 351        }
 352
 353        /*
 354         * Average periodic refresh interval
 355         * tREFI = 7.8 us at normal temperature range
 356         */
 357        pdimm->refresh_rate_ps = 7800000;
 358
 359        for (i = 0; i < 18; i++)
 360                pdimm->dq_mapping[i] = spd->mapping[i];
 361
 362        pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
 363
 364        return 0;
 365}
 366